Anritsu MT8801C - Bit Definition of END Event Status Register

5-15
5.5.1 Bit definition of END event status register
The following describes the operation of the END event status register model, the
naming of its event bits, and what they mean.
disabled = 0, enabled = 128(2
7
)
disabled = 0, enabled = 64 (2
6
)
disabled = 0, enabled = 32 (2
5
)
disabled = 0, enabled = 16 (2
4
)
disabled = 0, enabled = 8 (2
3
)
disabled = 0, enabled = 4 (2
2
)
disabled = 0, enabled = 2 (2
1
)
disabled = 0, enabled = 2 (2
0
)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
&
Logical OR
END Event Status Enable Register
Set by ESE2 <n>
Read by ESE2?
Read by ESR2?
END Event Status Register
ESB summary message bit
(To bit 2 of the status byte register)
Not used
Output level setting end
Not used
AVERAGE end
Not used
Not used
Calibration end
Sweep or measurement end
The END event status register selects whether the register makes the summary mes-
sage true when the corresponding bit of the status register is set.
Bit Event name Description
7 (Not used)
(Not used)
(Not used)
(Not used)
(Not used) (Not used)
(Not used) (Not used)
6 Output level setting end This bit is set to 1 when output level setting ends.
5
4 AVERAGE end This bit is set to 1 when averaging ends.
3
2
1 CAL end
This bit is set to 1 when calibration (Zero Set, Adjust Range
and Manual Calibration) ends.
0
Sweep or measurement end This bit is set to 1 when sweep or measurement ends.
5.5 Extended Event Status Register