Anritsu MT8801C - Extended Event Status Register

Section 5 Status Messages
5-14
5.5 Extended Event Status Register
The register models of the status byte register, standard event status register and en-
able registers are mandatory for equipment conforming to the IEEE488.2 standard.
In IEEE488.2, status-byte-register bits 7 (DIO8), 3 (DIO4) to 0 (DIO1) are assigned to
status summary bits supplied by the extended-register and extended-queue models.
For the MT8801C, as shown in the diagram below, bits 7, 1 and 0 are unused; bits 2
and 3 are assigned to the END and ERR summary bits as the status-summary bits
supplied by the extended-register model. As the queue model is not extended, there is
only one type of queue: the output queue.
MSS RQS
Not used
ESB
MAV
ERR
END
Not used
Not used
Service Request generation
Status byte register
Status summary
message
Standard event
status register
model
END event
status register
model
Data Data Data Data Data
......Output queue
Standard event summary bit
MAV summary bit
END event summary bit
7
6
5
4
3
2
1
0
Bit
ERR event
status register
model
ERR event summary bit
The following pages describe bit definition, the reading, writing to and clearing of bits
for the END extended event register model.