Anritsu MT8801C - IEEE488.2 Standard Status Model

5-3
5.1 IEEE488.2 Standard Status Model
5.1 IEEE488.2 Standard Status Model
The diagram below shows the standard model for the status data structure stipulated in
the IEEE488.2 standard.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
&
&
&
&
&
&
&
7
5
4
3
2
1
0
7
6
5
4
3
2
1
0
&
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&
&
Logical OR
Logical OR
Service Request
Generation
MSS 6 RQS
Standard event status
enable register
Set by ∗ESE <n>
Read by ∗ESE?
Service request enable register
Set by ∗SRE n
Read by ∗SRE?
Read by ∗ESR?
Read by serial port
Read by ∗STB?
Power on (PON)
User request (URQ, not used)
Command error (CME)
Execution error (EXE)
Device-dependent error (DDE)
Query error (QYE)
Request for bus control (RQC, not used)
Operation complete (OPC)
Standard event status register
Data
Data
Data
Data
Data
Data
Output Queue
Status summary message
Status byte
register
Standard Status Model Diagram
ESB
MAV