Section 5 Status Messages
5-8
(3) Definition of MSS (Master Summary Status)
MSS indicates that there is at least one cause for a service request. The MSS
message is represented by bit 6 in a device response to the *STB? query, but it is
not generated response to serial poll. In addition, it is not part of the status byte
specified by IEEE488.1.MSS is generated by the logical OR operation of the
STB register with SRQ enable (SRE) register. In concrete terms, MSS is de-
fined as follows:
(STB Register bit0 AND SRE Register bit 0)
OR
(STB Register bit1 AND SRE Register bit 1)
OR
:
:
(STB Register bit5 AND SRE Register bit 5)
OR
(STB Register bit7 AND SRE Register bit 7)
Since bit-6 status of the STB and SR enable registers is ignored in the definition
of MSS, it can be considered that bit-6 status is always being 0 when calculating
the value of MSS.
(4) Clearing the STB register by the *CLS common command
With the exception of the output queue and its MAV summary message, the
*CLS common command clears all status data structures (status event registers
and queues) as well as the corresponding summary messages.
The *CLS command does not affect settings in the enable registers.
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