BL702/704/706 Reference Manual
• In particular, if it is the last valid receiving BD, the WR bit needs to be set, and EMAC will ”wrap around” to the first
receiving BD for processing after processing this BD
• If there are multiple BDs available to receive data, repeat the steps of setting BD to fill all BDs
• If you need to enable the receive interrupt, you also need to configure the RX related bits in the EMAC_INT_MASK
register
• Configure the RXEN bit in the EMAC_MODE register to enable reception
• If the interrupt is enabled, in the received interrupt, the current BD can be obtained through the RXBDNUM field
in the EMAC_TX_BD_NUM register
• Perform corresponding processing according to the current BD status word
• For the received BD, the E bit in the control field will be cleared by hardware and will not be used for receiving
again; the data needs to be taken away, and E is set, this BD can be used for receiving again
17.8 Register description
Name
Description
MODE EMAC configuration
INT_SOURCE EMAC transmit control
INT_MASK EMAC interrupt mask
IPGT Inter packet gap
PACKETLEN Frame length
COLLCONFIG Collision configuration
TX_BD_NUM TX buffer descriptors number
MIIMODE Management Data configuration
MIICOMMAND Trigger command
MIIADDRESS Register address
MIITX_DATA Control data to be written to PHY
MIIRX_DATA Received data from PHY
MIISTATUS MIIM I/F status
MAC_ADDR0 Ethernet MAC address0
MAC_ADDR1 Ethernet MAC address1
HASH0_ADDR Lower 32-bit of HASH register
HASH1_ADDR Upper 32-bit of HASH register
BL702/704/706 Reference Manual 295/ 375
@2021 Bouffalo Lab
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