GR740-UM-DS, Nov 2017, Version 1.7 136 www.cobham.com/gaisler
GR740
12.9.5 TLB/cache flush register
Table 134.0x14 - FLUSH - TLB/cache flush register
31 87 43210
RESERVED FGRP RES GF F
00000
r rw r rw rw
31:1 RESERVED
7:4 Flush Group (FGRP) - This field specifies the group to be used for a Group Flush, see GF field
below.
3:2 RESERVED
1 Group Flush (GF) - When this bit is written to ‘1’ the cache entries for the group selected by the
FGRP field will be flushed. More precisely the core will use the FGRP field as (part of the) set
address when performing the flush. This flush option is only available if the core has support for
group set addressing (CA field of Capability register 1 is non-zero). This flush option must only be
used if the GS bit in the Control register is set to ‘1’, otherwise old data may still be marked as valid
in the Access Protection Vector cache or IOMMU TLB. This bit will be reset to ‘0’ when a flush
operation has completed. A flush operation also affects the FL and FC fields in the Status register.
0 Flush (F) - When this bit is written to ‘1’ the core’s internal cache will be flushed. This bit will be
reset to ‘0’ when a flush operation has completed. A flush operation also affects the FL and FC fields
in the Status register.
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