GR740-UM-DS, Nov 2017, Version 1.7 214 www.cobham.com/gaisler
GR740
Table 236. 0x0 - GRETH_GBIT control register
31 30 28 27 26 25 24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EA BS GA MA MC RESERVED ED RD DD ME PI BM GB SP RS PM FD RI TI RE TE
1 0b010 1 1 1 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r r r r r rw rw rw rw rw rw rw rw wc rw rw rw rw rw rw
31 EDCL available (EA) - Set to one if the EDCL is available.
30: 28 EDCL buffer size (BS) - Shows the amount of memory used for EDCL buffers. 1 = 2 KiB
27 Gigabit MAC available (GA) - This bit always reads as a 1 and indicates that the MAC has 1000
Mbit capability.
26 Mdio interrupts enabled (MA) - Set to one when the core supports mdio interrupts..
25 Multicast available (MC) - Set to one when the core supports multicast address reception.
24: 15 RESERVED
14 EDCL Disable (ED) - Set to one to disablethe EDCL and zero to enable it. Reset value taken from
the external DSU_EN signal. If DSU_EN is high then this bit will be low, and the EDCL will be
enabled after reset. Otherwise the EDCL will be disabled after reset.
13 RAM debug enable (RD) - RAM debug access is not available in this design. This bit is always zero.
Writes have no effect.
12 Disable duplex detection (DD) - Disable the EDCL speed/duplex detection FSM. If the FSM cannot
complete the detection the MDIO interface will be locked in busy mode. If software needs to access
the MDIO the FSM can be disabled here and as soon as the MDIO busy bit is 0 the interface is avail-
able. Note that the FSM cannot be re-enabled again.
11 Multicast enable (ME) - Enable reception of multicast addresses.
10 PHY status change interrupt enable (PI) - Enables interrupts for detected PHY status changes.
9 Burstmode (BM) - When set to 1, transmissions use burstmode in 1000 Mbit Half-duplex mode
(GB=1, FD = 0). When 0 in this speed mode normal transmissions are always used with extension
inserted. Operation is undefined when set to 1 in other speed modes.
8 Gigabit (GB) - 1 sets the current speed mode to 1000 Mbit and when set to 0, the speed mode is
selected with bit 7 (SP).
7 Speed (SP) - Sets the current speed mode. 0 = 10 Mbit, 1 = 100 Mbit. Must not be set to 1 at the same
time as bit 8 (GB).
6 Reset (RS) - A one written to this bit resets the GRETH_GBIT core. Self clearing. No other accesses
should be done .to the slave interface other than polling this bit until it is cleared.
5 Promiscuous mode (PM) - If set, the GRETH_GBIT operates in promiscuous mode which means it
will receive all packets regardless of the destination address.
4 Full duplex (FD) - If set, the GRETH_GBIT operates in full-duplex mode otherwise it operates in
half-duplex.
3 Receiver interrupt (RI) - Enable Receiver Interrupts. An interrupt will be generated each time a
packet is received when this bit is set. The interrupt is generated regardless if the packet was
received successfully or if it terminated with an error.
2 Transmitter interrupt (TI) - Enable Transmitter Interrupts. An interrupt will be generated each time a
packet is transmitted when this bit is set. The interrupt is generated regardless if the packet was
transmitted successfully or if it terminated with an error.
1 Receive enable (RE) - Should be written with a one each time new descriptors are enabled. As long
as this bit is one the GRETH_GBIT will read new descriptors and as soon as it encounters a disabled
descriptor it will stop until RE is set again. This bit should be written with a one after the new
descriptors have been enabled.
0 Transmit enable (TE) - Should be written with a one each time new descriptors are enabled. As long
as this bit is one the GRETH_GBIT will read new descriptors and as soon as it encounters a disabled
descriptor it will stop until TE is set again. This bit should be written with a one after the new
descriptors have been enabled.
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