COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 300 www.cobham.com/gaisler
GR740
Table 375.0xn4 where n selects the timer - TRLDVALn - Timer n counter reload value register
31 0
TRLDVAL
*
rw
31: 0 Timer Reload value (TRLDVAL) - This value is loaded into the timer counter value register when
‘1’ is written to the TCTRL.LD load bit or when the TCTRL.RS bit is set and the timer underflows.
This field is set to 0xFFFF for the watchdog timer. The reset value is undefined for the other timers.
Table 376.0xn8 where n selects the timer - TCTRLn - Timer n control register
31 9876543210
RESERVED WS WN DH CH IP IE LD RS EN
0 000*0****
r rw*rw r rwwcrwrwrwrw
31: 9 RESERVED
8 Disable Watchdog Output (WS/WDOGDIS) - If this field is set to ’1’ then the watchdog output will
not be affected by the timer unit. This field is only available for the last timer of timer unit 0.
7 Enable Watchdog NMI (WN/WDOGNMI) - If this field is set to ’1’ then the watchdog timer will
also generate a non-maskable interrupt (interrupt 15) when an interrupt is signaled. This field is only
available for the last timer of timer unit 0.
6 Debug Halt (DH): Value of internal signal that is used to freeze counters (e.g. when a system is in
debug mode).
5 Chain (CH): Chain with preceding timer. If set for timer n, timer n will be decremented each time
when timer (n-1) underflows.
This field is reset to ’0’ for the watchdog timer. It is not reset for the other timers.
4 Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt is signalled. This bit remains ‘1’
until cleared by writing ‘1’ to this bit, writes of ‘0’ have no effect.
3 Interrupt Enable (IE): If set the timer signals interrupt when it underflows.
This field is reset to ’1’ for the watchdog timer. It is reset to ’0’ for the other timers.
2 Load (LD): Load value from the timer reload register to the timer counter value register. This bit is
automatically cleared when the value has been loaded.
This field is reset to ’1’ for the watchdog timer. It is not reset for the other timers.
1 Restart (RS): If set, the timer counter value register is reloaded with the value of the reload register
when the timer underflows.
This field is reset to ’0’ for the watchdog timer. It is not reset for the other timers.
0 Enable (EN): Enable the timer.
The watchdog timer (GPTIMER 0, timer 5) is disabled after reset if external signal BREAK = LOW
or if the DSU is enabled via external signal DSU_EN = HIGH.
Table 377.0xnC where n selects the timer - TLATCHn - Timer n latch register
31 0
LTCV
0
r
31: 0 Latched timer counter value (LTCV): Valued latched from corresponding timer.

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English