1-2 Compaq AlphaServer ES40 Service Guide
1.1
System Architecture
The system uses a switch-based interconnect system that maintains
constant performance even as the number of transactions multiplies.
Figure 1–1 System Block Diagram
C-chip
First
CPU
8 D-chips
P-chip
P-chip
1 or 2
Memory
Arrays
Memory
Arrays
64 bit PCI
64 bit PCI
Command, Address, and Control lines for each Memory Array
Control lines for D-chips
Memory
Data
Bus
CPU
Data
Bus
CAPbus
PAD
Bus
PKW1400A-99
1 or 2
CPUs
B-cache
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