Registers D-5
Table D–2 Memory Management Status Register Fields
Name Bits Type Description
Reserved <63:11> Reserved for Compaq.
DC_TAG_
PERR
<10> RO
This bit is set when a D-cache tag parity error
occurs during the initial tag probe of a load or
store instruction. The error created a
synchronous fault to the D_FAULT PALcode
entry point and is correctable. The virtual
address associated with the error is available in
the VA register.
OPCODE <9:4> RO Opcode of the instruction that caused the error.
HW_LD is displayed as 3 and HW_ST is
displayed as 7.
FOW <3> RO
Set when a fault-on-write error occurs during a
write transaction and PTE[FOW] was set.
FOR <2> RO Set when a fault-on-read error occurs during a
read transaction and PTE[FOR] was set.
ACV <1> RO
Set when an access violation occurs during a
transaction. Access violations include a bad
virtual address.
WR <0> RO Set when an error occurs during a write
transaction.
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