Registers D-35
D.14
21272-CA Array Address Registers (AAR0–AAR3)
The Array Address Registers define the base address and size for each
memory array.
Table D–13 21272-CA Array Address Register (AAR)
Field Bits Type Init Description
RES
<63:35> MBZ,RAZ 0 Reserved.
ADDR
<34:24> RW 0 Base address – Bits <34:24> of the physical
byte address of the first byte in the array.
(<34:32> are used in Typhoon only; <34:28>
are valid)
RES
<23:17> MBZ,RAZ 0 Reserved.
DBG
16 RW 0 Enables this memory port to be used as a debug
interface.
ASIZ
<15:12> RW 0 Array size (<15> is used in Typhoon only).
Value Size
0000 0 (bank disabled)
0001 16MB
0010 32MB
0011 64MB
0100 128MB
0101 256MB
0110 512MB
0111 1GB
1000 2GB (Typhoon only)
1001 4GB (Typhoon only)
1010 8GB (Typhoon only)
1011 1111 Reserved.
RES
<11:10> MBZ,RAZ 0 Reserved.
TSA
<9> RW 0 Twice-split array (Typhoon only)
SA
<8> RW 0 Split array.
Continued on next page