D-20 Compaq AlphaServer ES40 Service Guide
Table D–8 I_CTL Register Fields (Continued)
Name Extent Type Description
PCT0_EN [18] RW,0 Enable performance counter #0. If this bit is
one, the performance counter will count if
EITHER the system (SPCE) or process
(PPCE) performance counter enable is set.
SINGLE_ISSUE_H [17] RW,0 When set, this bit forces instructions to
issue only from the bottom-most entries of
the IQ and FQ.
VA_FORM_32 [16] RW,0
This bit controls address formatting on a
read of the IVA_FORM register.
VA_48 [15] RW,0 This bit controls the format applied to
effective virtual addresses by the
IVA_FORM register and the Ibox virtual
address sign extension checkers. When
VA_48 is clear, 43-bit virtual address format
is used, and when VA_48 is set, 48-bit
virtual address format is used. The effect of
this bit on the IVA_FORM register is
identical to the effect of VA_CTL[VA_48] on
the VA_FORM register.
When VA_48 is set, the sign extension
checkers generate an ACV if va[63:0]
≠
SEXT(va[47:0]). When VA_48 is clear, the
sign extension checkers generate an ACV if
va[63:0]
≠
SEXT(va[42:0]).
This bit also affects DTB_DOUBLE Traps. If
set, the DTB double miss traps vector to the
DTB_DOUBLE_4 entry point.
DTB_DOUBLE PALcode flow selection is
not affected by VA_CTL[VA_48].
SL_RCV [14] RO
When in native mode, any transition on
SL_RCV, driven from the SromData_H pin,
results in a trap to the PALcode interrupt
handler. When in PALmode, all interrupts
are blocked. The interrupt routine then
begins sampling SL_RCV under a software
timing loop to input as much data as
needed, using the chosen serial line protocol.
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