System Overview 1-19
PCI Bus Implementation
•
Is fully compliant with the PCI Version 2.1 Specification
•
Operates at 33 MHz, delivering a peak bandwidth of 500 MB/sec; over 250
Mbytes/sec for each PCI bus
•
Has six option slots (Model 1) or ten option slots (Model 2)
•
Supports three address spaces: PCI I/O, PCI memory, and PCI configuration
space
•
Supports byte/word, tri-byte, quadword, and longword operations
•
Exists in noncached address space only
I/O Implementation
In a system with 10 I/O slots, PCI 0 has 4 slots, and PCI 1 has 6 slots. In a
system with 6 slots, each PCI has 3 slots; the middle four connectors are not
present.
The Acer Labs 1543C chip provides the bridge from PCI 0 to ISA. The C-chip
controls accesses to memory on behalf of both P-chips.
I/O Ports
The I/O ports are shown in Section 1.5.
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