Registers D-51
Table D–21 Bit Definition of Logout Frame Registers (Continued)
Register
Identification Bit Field Text Translation Description
I_CTL <2:1>
<7:6>
<13>
<14>
<15>
<20>
<21>
<29:24>
<47:30>
01(Bin) and 10(Bin) for Icache set 1 or 2 enabled, respectively
01(Bin) and 10(Bin) for R8-R11 & R24-R27 and R4-R7 & R20-
R23 are used for PAL shadow registers, respectively
Set = forces bad Icache tag parity
Set = forces bad Icache data parity
Clear and set for 43 bit or 48 bit virtual address format,
respectively
Clear or set for R23 or R27 used as CALL_PAL linkage
register, respectively
Set to enable machine check processing
Revision ID number for EV6 Chip as follows: 01(Hex) = Pass
1.0; 02(Hex) = Pass 2.2; 03(Hex) = Pass 2.3; 0x04 (Hex) = Pass
3.0.
Virtual page table base address
PCTX
<0>
<1>
<2>
<4:3>
<8:5>
<12:9>
<38:13>
<46:39>
<63:47>
Ibox process context register as follows :
Reserved/RAZ
If set, both performance counters are enabled
If clear , floating-point instructions generate FEN
exceptions
Reserved/RAZ
Enable AST U,S,E,K interrupt requests
Request AST U,S,E.K interrupts
Reserved/RAZ
Address Space Number
Reserved/RAZ
Software Error
Summary Flags <0>
<1>
<2>
<63:3>
PAL,HAL, and OS Error handler signaling software flags
Set = Pchip0 P_Error<9:0> error has occurred.
Set = Pchip1 P_Error<9:0> error has occurred.
Set = Pchip0 or Pchip1 P_Error <11/10>
uncorrectable/correctable error, or CPU correctable error, or
CPU uncorrectable error has occurred.
Unused
To Next Page
Loading...
Need help?
General
