Efinix Titanium - Page 81

Titanium Interfaces User Guide
lvds_rule_rx_clock (error)
Message Serial and parallel clocks cannot be the same clock
To fix You cannot use the same clock for both the serial (FASTCLK) and parallel (SLOWCLK) clocks.
Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.
Message Serial and parallel clocks are not from the same PLL instance
To fix You need to use the same PLL to generate both clocks.
Message Invalid phase shift difference: <phase diff> = Serial: <value> - Parallel: <value> (Min=45
degress, Max=135 degrees)
To fix The phase shift for the parallel and serial clocks must be between 45° and 135°.
Message One of the clock frequencies is 0
To fix The output clock frequency is invalid. Check that the PLL is configured correctly.
Message Serial clock frequency has to be <float> times faster than parallel clock
To fix Make sure that the PLL output clock frequencies are set correctly.
Half rate calculation—serial clock frequency = parallel clock frequency * (serialization / 2)
Full rate calculation—serial clock frequency = parallel clock * serialization
lvds_rule_rx_clock_region (error)
Message Serial and Parallel clocks generated by PLL have to be driven to the same clock network.
<Serial|Parallel> clock <name> was generated by PLL output clock 4 that connects to regional
clock network
To fix In Ti35 and Ti60FPGAs, the PLL's output clock 4 can only drive the regional clock network.
You should use the other clock outputs for the serial and parallel clocks.
lvds_rule_rx_config (error)
Message Input name must be configured
To fix Specify a valid pin name.
Message Serial clock name must be configured
To fix When you are using the LVDS deserializer (deserialization width greater than 1), you need to
specify the serial clock pin name.
Message Parallel clock name must be configured
To fix When you are using the LVDS deserializer (deserialization width greater than 1), you need to
specify the parallel clock pin name.
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