Efinix Titanium - Page 97

Titanium Interfaces User Guide
The clock lane generates the fast clock and slow clock for the RX data lanes within the
interface group. It also generates a clock that feeds the global network. The following figure
shows the clock connections between the clock and data lanes.
Figure 36: Connections for Clock and RX Data Lane
Clock Lane
Programmable
Delay
Configuration
Setting
Div4
FASTCLKOUT (1)
SLOWCLKOUT (1)
CLKOUT
Data Lane
Deserializer
SLOWCLK (1)
FASTCLK (1)
Programmable
Delay
Up/Down Counter
FIFO
Configuration
Setting
To Global
Network
From Buffer
From Buffer
To Core
FIFOCLK (1)
1. The software automatically connects this signal for you.
From Global
Network
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