Inovance H3U Series - MXNR Matrix XNR Operation

223
4
4 Instructions 4.6.1 Matrix Operations
MXNR: Matrix XNR operation
◆
Overview
The MXNR instruction performs XNR operation in matrix format.
MXNR S1 S2 D n
Matrix XNR
operation
Applicable model:
H3U
S1 Matrix 1 Operand element 1 in an operation
16-bit instruction (9
steps)
MXNR: Continuous
execution
MXNRP: Pulse
execution
S2 Matrix 2 Operand element 2 in an operation
D
Operation
result
Start number of elements that store the operation
result
n Data count
Number of data entries in an operation; value range:
1 to 256
◆
Operands
Operand
Bit Element Word Element
System·User System·User Bit Designation Indexed Address Constant
Real
Number
S1 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
S2 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
D X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
Note: The elements in gray background are supported.
◆
Function
An XNR operation is performed on the bit patterns of the n bytes of data from head addresses [S1] and [S2].
The result is stored in elements from head address [D].
The result is 1 when the values of two bits are the same; otherwise, the result is 0.
Assume that n = 4. The result of a matrix XNR operation is as follows:
1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0
1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1
1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0
1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0
1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0
1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0
bit15 bit0
[+1]
[S1+0]
[+2]
[+3]
[+1]
[S2+0]
[+2]
[+3]
[+1]
[D+0]
[+2]
[+3]
(bit XNR)