Inovance H3U Series - High-Speed Counter; Register; Data Register D

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3
3 Elements3.7 Register
3.6.3 High-speed Counter
High-speed counters can be used for counting external input signals and supports single-phase sin-
gle-counting, single-phase dual-counting, and A/B-phase fundamental or quadruplicated frequency. For
details about use of high-speed counters, see
“Chapter 5 High-speed Input” on page 336
.
3.7 Register
Registers are used for data computation and storage of parameters of timers, counters, and analog values. The
width of each register is 16-bit. When a 32-bit instruction is used, the two neighboring registers are automatically
combined into a 32-bit register, with the lower address being used as the low-order byte, and the higher address
being used as the high-order byte.
The H3U supports the data register D, address indexing data registers V and Z, and le register R.
For general
purpose
For retention
purpose
For retention
purpose
For special
purpose
For
address
indexing
purpose
For retention
purpose
For special
purpose
D0 to D199
200 points
[1]
D200 to D511
312 points
[2]
D512 to D7999
7488 points
[3]
D8000 to D8511
512 points
V0 to V7
Z0 to Z7
R0 to R32767
32,768 points
[3]
SD0 to SD1023
1024 points
• [1] It cannot be retained upon power failure. It can be set to be retained upon power failure through parameter
setting.
• [2] It can be retained upon power failure. It can be set to be not retained upon power failure through parameter
setting.
• [3] It can be retained upon power failure and the status cannot be modied through parameter setting.
3.7.1 Data Register D
The width of each data register D is 16-bit. When 32-bit data is used, the two neighboring data registers
D are combined to demonstrate 32-bit data. (The bigger D register is the higher 16 bits, and the smaller
D register is the lower 16 bits. In an address indexing register, V is the higher bit, and Z is the lower bit.)
When the lower bit (for example, D0) of the 32-bit register is specied, the higher-bit number (for example,
D1) following the lower bit is automatically occupied. You can use an odd or even number of any element
to specify the lower bit. Considering the monitoring function of peripheral devices, it is suggested using an
even number of an element to specify the lower bit.
For a data register which cannot be retained upon power failure, no change occurs as long as no other data
is written into the register after initial data writing. However, when the slide switch of PLC switches from
RUN to STOP or PLC power off, all data will be cleared. (The data can be retained if the special auxiliary
relay M8033 is driven.) If the data register is of power failure retain type, the data can be retained when the
slide switch of PLC switches from RUN to STOP or PLC power off.
You can modify the allocation of D registers for general purpose use or retention purpose use by setting
system parameters. When data registers dedicated for retention upon power failure are used for general
purpose, use the RST or ZRST instruction to clear their content when starting the project.