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4
4 Instructions4.11.2 Verication
●
Example:
〔CCD D100 D10 K7〕
X15
S D n
The M8161 ag determines which variable width mode to use. When M8161 = OFF, the 16-bit mode is
enabled, whereby the higher and lower bytes of variables are taken for the operation. When M8161 = ON,
the 8-bit mode is enabled, whereby only the lower bytes of variables are taken for the operation and the
higher bytes are discarded. Therefore, the length of the actually used variable area is increased. See the
following gure.
Summation is the process where the values of n variables are added together.
The XOR logical operation is described as follows:
1) The variables are converted to binary numbers.
2) Bit 0 = 1 occurrences in all variables are counted. If the counting result is an even number, the XOR
operation result for bit 0 is 0; if the counting result is an odd number, the XOR operation result for bit 0
is 1.
3) Then bit 1 = 1 occurrences in all variables are counted. If the counting result is an even number, the
XOR operation result for bit 1 is 0; if the counting result is an odd number, the XOR operation result for
bit 1 is 1.
4) The counting proceeds to bit 2 through bit 7. The resulting binary number is converted to a hexadecimal
equivalent, which is the XOR operation result (or called a polarity value).
+ +
$+ +
)+ +
'+ +
$+ +
&+ +
+ $+
D100
D101
D102
D103
M8161 = OFF, 16-bit mode
M8161 = ON, 8-bit mode
n
H L
D104
D105
D106
+ +
D100
D101
D102
D103
S
n
$+ +
)+ +
'+ +
H L
D104
$+ +
D105
&+ +
D106
+ $+
For example, the data
from head address
D100 is as follows:
&+
D10
D11
(+
D10
D11
Cumulative sum:
XOR (polarity):
Cumulative sum:
XOR (polarity):
The RS, HEX, ASCI, and CCD instructions share the M8161 ag. Pay attention to the ag processing
during programming.
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