Inovance H3U Series - Page 344

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5
5 High-speed Input 5.2.1 HSCS Comparison Setting
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Instruction for use:
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Before the HSCS instruction is executed, the counter used must have been enabled (see Example 1); otherwise,
the value of the counter will not change.
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The counter responds to input signals in interrupt mode and timely compare values. If the compared values are
matched, the comparison output is immediately set. In Example 1, when the present value of C255 changes from
99 to 100 or from 101 to 100, Y10 is set immediately and remains in that state. Even if values of C255 and K100
are not equal by comparison, Y10 remains ON, unless there is an additional reset operation.
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The comparison output of the instruction only depends on the comparison result at the pulse input. Without
the pulse input, even if the DMOV or DADD instruction is executed to rewrite the content of C235-C255 high-
speed counters, the comparison output will not change. Flows driven by instructions cannot simply change the
comparison result.
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When the target output of the HSCS instruction is counter interrupts I010-I080, each interrupt number can be used
for only once rather than reused. See the previous section for settings and use of counter interrupts.
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Like common instructions, HSCS, HSCR, and HSZ can be executed repeatedly, but there should be less than
eight simultaneously active instructions. Only one HSZ instruction in special mode (high-speed table comparison
mode or frequency control mode) can be active.
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Example
1
:
Action delay of Y10 related to the scan cycle
Immediate output of Y10
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Example
2
:
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Main program:
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I010 interrupt subprogram
The D operand range of the DHSCS instruction can also be specied to I0x0 (x=1-8). When the counter
reaches the set value, interrupt routines are triggered.
If M8059 is set to ON, all high-speed counter interrupts are disabled.
Differences of the ON signal on D operand with I010 or Y, M, or S outputs:
The program is running
The program
is running
The program
is running