Inovance H3U Series - Page 355

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5
5 High-speed Input5.3.1 High-speed Counter
Bx
Ax
A
/B phase counting up at a quadruplicated frequency
+1
+1
+1
+1
+1
+1
+1
+1
Bx
Ax
A/B phase counting down at a quadruplicated frequency
-1
-1
-1
-1
-1
-1
-1
-1
Bx
A
x
CW/CCW counting
+1
+1
+1
-1
-1
-1
3
)
Use of counters
●
High-speed counters use hardware for counting based on the transition edge of relevant signals, and provide real-
time responses, independent of the scan duration of the PLC.
●
When the present value of a high-speed counter reaches the set value, for immediate output and processing,
execute high-speed pulse comparison instructions, such as HSCS, HSCR, and HSZ. For details, see the
interpretation of instructions.
●
When the present value of a high-speed counter reaches the set value, for immediate logical processing, execute
the high-speed pulse comparison instruction HSCS, and specify the instruction operation to I0x0 interrupt (x
= interrupt numbers 1–8), provided that subprograms corresponding to interrupt numbers must have been
programmed.
●
The software lter time of high-speed input signals can be set by setting element to D8021 and the time unit to
250 ns. The default value of D8021 is 1, so the default high-speed lter time is 250 ns. The value range of D8021
is 1 to 100, so the high-speed lter time range is 0.25 to 25 us.