WEB Interface 75
ID: um_t2gateway CP560 DVB-T2 Gateway User’s Manual Rev. 2.2 (3686)
8.4.6 Clock Regulator
This page lets the user configure synchronisation of the internal 27 MHz clock from an external
source.
8.4.6.1 Main
Figure 8.29 Clock regulator
The reference signal is supplied on a separate connector. This page gives access to selecting
how the reference is used.
The Configuration field:
27 MHz lock mode
Disabled
The internal clock will not make use of an external reference signal.
Lock to external 1 PPS
Configures the internal clock to use the external 1 PPS input connector as reference.
The Clock Regulator Status field:
Regulator state
Idle
External reference signal is disabled.
Waiting
External Reference signal is enabled, but the internal clock has not obtained lock to
the reference
Fine tune
External Reference signal is enabled, and the internal clock has obtained lock to the
reference.
Current phase offset
Phase offset between the internal clock and 1 PPS clock reference given as a multiple of
3.704 ns (one period of 270 MHz)
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