Xilinx Virtex-4 Configuration User Guide

14 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 1: Configuration Overview
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The terms Master and Slave refer to the direction of the configuration clock (CCLK):
• In Master configuration modes, the Virtex-4 device drives the configuration clock
(CCLK) from an internal oscillator
• In Slave configuration modes, the configuration clock is an input.
The JTAG/Boundary-Scan configuration interface is always available, regardless of the
MODE pin settings. The JTAG/Boundary-Scan configuration mode disables all other
configuration modes. This prevents conflicts between configuration interfaces.
The JTAG interface is available after the mode pins are sampled. Activating PROGRAM_B
disables JTAG until INIT is completed.
Certain pins are dedicated to configuration, while others are dual-purpose (Table 1-2).
Dual-purpose pins serve both as configuration pins and as user I/O after configuration.
Dedicated configuration pins retain their function after configuration.
Table 1-2: Virtex-4 Configuration Pins
Pin Name Type
(1)
Dedicated or
Dual-Purpose
(2)
Description
M[2:0] Input Dedicated Mode pins that determine configuration mode. Sampled on the rising
edge of INIT_B.
CCLK Input or
Output
Dedicated Configuration clock source for all configuration modes except JTAG.
D_IN Input Dedicated Serial data input for serial configuration modes.
DOUT_BUSY Output Dedicated In Serial configuration mode, pin acts as serial data output for daisy-chain
configuration. In SelectMAP mode, pin acts as BUSY output.
DONE Bidirectional,
Open-Drain
or Active
Dedicated Active High signal indicating configuration is complete.
0 = FPGA not configured
1 = FPGA configured
Refer to the “BitGen” section of the Development System Reference Guide for
software settings.
INIT_B Input or
Output,
Open-Drain
Dedicated Before MODE pins are sampled, INIT_B is an input that can be held Low
to delay configuration.
After MODE pins are sampled, INIT_B is an open-drain active Low
output indicating whether a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
PROGRAM_B Input Dedicated Active Low asynchronous full-chip reset.
SelectMAP
Data
Bidirectional Dual-Purpose Parallel data inputs for SelectMAP modes.
For 8-bit SelectMAP:
D0 = MSB
D7 = LSB
For 32-bit SelectMAP:
D0 = LSB
D31 = MSB

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English