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Xilinx Virtex-4 Configuration User Guide
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www.xilinx.com
Virtex-4 FPGA Con
figuration Use
r Guide
UG071 (v1.12) June 2, 20
17
Chapter 3:
Boundary-Scan and JTAG Configuration
R
Figure 3-
6:
Device Configuration Flow Diagram
Sa
mple
Mode Pin
s
JT
A
G A
v
a
il
ab
le
K
eep Cle
a
ring
Config
u
r
a
tion
Memory
No
No
Ye
s
Ye
s
Ye
s
Ye
s
No
Ye
s
Cle
a
r Config
u
r
a
tion
Memory Once More
P
ower-Up
V
CCINT
> 1.0
V
CRC
Correct?
Lo
a
d CFG_IN
In
s
tr
u
ction
Lo
a
d
Bit
s
tre
a
m
A
b
or
t
S
t
a
rt
u
p
S
h
u
tdown
S
e
qu
ence
Reconfig
u
re?
Lo
a
d J
S
TA
R
T
In
s
tr
u
ction
S
ynchrono
us
T
AP Re
s
et
S
t
a
rt
u
p
S
e
qu
ence
Oper
a
tion
a
l
INIT_B = High?
PROGRAM_B
Low?
u
g071_40_073007
Lo
a
d
J
S
HUTDOWN
In
s
tr
u
ction
No
(Clock fiv
e 1
s
on
TM
S
)
67
69
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
5
Preface: about this Guide
9
Guide Contents
9
Additional Documentation
9
Additional Resources
10
Typographical Conventions
10
Online Document
11
Chapter 1: Configuration Overview
13
Introduction
13
Setup (Steps 1-3)
15
Device Power-Up (Step 1)
15
Clear Configuration Memory (Step 2, Initialization)
16
Sample Mode Pins (Step 3)
17
Delaying Configuration
17
Bitstream Loading (Steps 4-7)
18
Synchronization (Step 4)
18
Check Device ID (Step 5)
19
Load Configuration Data Frames (Step 6)
20
Cyclic Redundancy Check (Step 7)
20
Startup (Step 8)
21
Bitstream Encryption
23
AES Overview
23
Creating an Encrypted Bitstream
24
Loading the Encryption Key
24
Loading Encrypted Bitstreams
24
Bitstream Encryption and Internal Configuration Access Port (ICAP)
25
Vbatt
25
Chapter 2: Configuration Interfaces
27
Serial Configuration Interface
27
Clocking Serial Configuration Data
29
Master Serial Configuration
29
Slave Serial Configuration
30
Serial Daisy Chains
30
Configuring a Serial Daisy Chain with a Microprocessor or CPLD
32
Mixed Serial Daisy Chains
33
Guidelines and Design Considerations for Serial Daisy Chains
33
Ganged Serial Configuration
37
Startup Sequencing (GTS)
38
Disable the Active DONE Driver on for All Devices
38
Connect All DONE Pins if Using a Master Device
38
DONE Pin Rise Time
38
Configuration Clock (CCLK) as Clock Signal for Board Layout
38
Signal Fanout
38
PROM Files for Ganged Serial Configuration
39
Selectmap Configuration Interface
39
Single Device Selectmap Configuration
41
Multiple Device Selectmap Configuration
42
Ganged Selectmap
44
Selectmap Data Loading
45
Continuous Selectmap Data Loading
46
Non-Continuous Selectmap Data Loading
48
Selectmap ABORT
49
Configuration Abort Sequence Description
49
Readback Abort Sequence Description
50
ABORT Status Word
50
Resuming Configuration or Readback after an Abort
51
Selectmap Reconfiguration
51
Selectmap Data Ordering
52
Configuration Data Files
53
Byte Swapping
53
Generating PROM Files
54
PROM Files for Serial Daisy Chains
54
PROM Files for Selectmap Configuration
55
Chapter 3: Boundary-Scan and JTAG Configuration
57
Introduction
57
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
57
Test Access Port
57
TAP Controller
59
Boundary-Scan Architecture
61
Boundary-Scan Register
61
Instruction Register
62
BYPASS Register
64
Identification Register
64
Configuration Register (Boundary-Scan)
66
USERCODE Register
66
USER1, USER2, USER3, and USER4 Registers
66
Using Boundary-Scan in Virtex-4 Devices
66
Configuring through Boundary-Scan
67
Reconfiguring through Boundary-Scan
70
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532
71
ISC Modal States
71
Clocking Startup and Shutdown Sequences (JTAG)
72
Configuration Flows Using JTAG
73
Chapter 4: Frame ECC Logic
75
Using Frame ECC Logic
75
Chapter 5: User Access Register
77
Using the User Access Register
77
Chapter 6: Reconfiguration Techniques
79
Dynamic Reconfiguration of Functional Blocks (DRP)
79
Background
79
Overview
79
FPGA Fabric Port Definition
80
DRP DCM Implementation
83
Changing the Multiply and Divide Values
83
Dynamic Phase Shifting through the DRP in Direct Mode
84
ICAP - Internal Configuration Access Port
85
Chapter 7 : Configuration Details
87
Configuration Memory Frames
87
Configuration Control Logic
88
Packet Types
88
Type 1 Packet
88
Type 2 Packet
89
Configuration Registers
89
Command Register (CMD)
90
Control Register (CTL)
91
Frame Address Register (FAR)
92
Status Register (STAT)
93
Configuration Options Register (COR)
94
Bitstream Composition
96
Default Initial Configuration Process
96
Chapter 8: Readback and Configuration Verification
99
Preparing a Design for Readback
99
Readback Command Sequences
100
Accessing Configuration Registers through the Selectmap Interface
100
Configuration Register Read Procedure (Selectmap)
101
Configuration Memory Read Procedure (Selectmap)
102
Accessing Configuration Registers through the JTAG Interface
104
Configuration Register Read Procedure - JTAG
104
Configuration Memory Read Procedure (1149.1 JTAG)
106
Configuration Memory Read Procedure (1532 JTAG)
109
Verifying Readback Data
110
Readback Capture
113
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Xilinx Virtex-4 Specifications
General
Brand
Xilinx
Model
Virtex-4
Category
Motherboard
Language
English
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