Xilinx Virtex-4 - Page 68

68 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 3: Boundary-Scan and JTAG Configuration
R
Figure 3-6: Device Configuration Flow Diagram
Sample
Mode Pins
JTAG Available
Keep Clearing
Configuration
Memory
No
No
Ye s
Ye s
Ye s
Ye s
No
Ye s
Clear Configuration
Memory Once More
Power-Up
V
CCINT
> 1.0 V
CRC
Correct?
Load CFG_IN
Instruction
Load
Bitstream
Abort Startup
Shutdown
Sequence
Reconfigure?
Load JSTA RT
Instruction
Synchronous
TAP Reset
Startup
Sequence
Operational
INIT_B = High?
PROGRAM_B
Low?
ug071_40_073007
Load
JSHUTDOWN
Instruction
No
(Clock five 1s
on TMS)