Xilinx Virtex-4 Configuration User Guide

82 www.xilinx.com Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Chapter 6: Reconfiguration Techniques
R
Table 6-1: Port Signal Definitions
Signal Name Direction
(1)
Description
DCLK Input
The rising edge of this signal is the timing reference for
all the other port signals. The required hold time for the
other input signals relative to the rising edge of DCLK
is zero (maximum). Normally, DCLK is driven with a
global clock buffer.
DEN Input
This signal enables all port operations. If DWE is
FALSE, it is a read operation, otherwise a write
operation. For any given DCLK cycle, all other input
signals are don't care if DEN is not active.
DWE Input
When active, this signal enables a write operation to the
port (see DEN, above).
DADDR[m:0] Input
The value on this bus specifies the individual cell that is
written or read on the next cycle of DCLK. The address
is presented in the cycle that DEN is active.
DI[n:0] Input
The value on this bus is the data that is written to the
addressed cell. The data is presented in the cycle that
DEN and DWE are active, and is captured in a register
at the end of that cycle, but the actual write occurs at an
unspecified time before DRDY is returned.
DO[n:0] Output
If DWE was inactive when DEN was activated, the
value on this bus when DRDY goes active is the data
read from the addressed cell. At all other times, the
value on DO[n:0] is undefined.
DRDY Output
This signal is a response to DEN to indicate that the DRP
cycle is complete and another DRP cycle can be
initiated. In the case of a port read, the DO bus must be
captured on the rising edge of DCLK in the cycle that
DRDY is active. The earliest that DEN can go active to
start the next port cycle is the same clock cycle that
DRDY is active.
Notes:
1. Input denotes input (write) to the DRP.

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English