Analog Devices ADRV9002 User Manual

Preliminary Technical Data UG-1828
Rev. PrB | Page 127 of 277
Transmitter Initial Calibrations Utilizing Internal Signal Generation Without Loopback
Figure 126 shows a high level block diagram of system configurations for transmitter initial calibrations requiring inserting signals into
the transmitter datapath without using loopback path.
DAC
DATA PORT
CMOS-SSI
OR
LVDS-SSI
FROM
BBP
DAC
LPF
LO1
LO2
LPF
PA
PA SWITCH OFF
24159-099
TX_PATH
DELAY
90°
0°
TX_BBAF
TX_BBAF_GD
SIGNAL
GENERATOR
Figure 126. Transmitter Initial Calibration System Configuration with Signal Generation Without Loop Back
As shown in Figure 126, an internal signal generator inserts calibration signals (red) into the transmitter datapath. The data port is
disabled during initial calibrations to avoid producing interference. TX_PATH_DELAY is performed in the digital domain, whereas
TX_BBAF and TX_BBAF_GD are performed in the analog domain. All of them use the signal generator to insert tones for calibration.
During all these calibrations, test signals inserted into the transmitter datapath can appear at the transmitter output, so it is important
that the power amplifier connected to the device output be switched off, which also prevents signals from the antenna reaching the
transmitter during calibrations. 50 Ω termination is also needed to prevent tone signals bouncing back from power amplifier input and
reaching the device transmitter output, thereby confusing internal calibrations. The following paragraph summarizes the external system
requirement.
External system requirement: for transmitter initial calibrations utilizing internal signal generation without loopback, the power
amplifier in the transmitter path should be powered off during these calibrations. When the power amplifier is disabled, the load seen at
the transmitter output should be 50 Ω.
Transmitter Initial Calibrations Utilizing Internal Signal Generation and ILB
Figure 127 shows a high level block diagram of system configurations for transmitter initial calibrations utilizing internal signal
generation and ILB path.
DAC
FROM
BBP
DAC
LPF
LO1
LO2
LPF
90°
0°
TX_LB_PD
TX_QEC
TX_LO_LEAKAGE
TX_DCC
TX_ATTEN_DELAY
TO
BBP
PA
PA SWITCH OFF
ILB
LNA SWITCH OFF
HP ADC
LP ADC
LP ADC
HP ADC
LPF
LO1
LO2
LPF
90°
0°
ADRV9001
LNA
DUPLEXER
(TDD,FDD)
24159-100
DATA PORT
CMOS-SSI
OR
LVDS-SSI
SIGNAL
GENERATOR
Figure 127. Tx Initial Calibration System Configuration with Signal Generation and Internal Loop Back
As shown in Figure 127, TX_LB_PD, TX_QEC, TX_LO_LEAKAGE, TX_DCC, and TX_ATTEN_DELAY use the ILB for calibrations.
TX_LO_LEAKAGE and TX_QEC calculate the initial correction parameters. TX_LB_PD provides a measurement of the loop back path
delay for TX_LO_LEAKAGE and TX_QEC algorithms. Both TX_LO_LEAKAGE and TX_QEC calibrations sweep through a series of

Analog Devices ADRV9002 Specifications

General

Frequency Range	30 MHz to 6 GHz
Number of Transmit Channels	2
Number of Receive Channels	2
Observation Receiver Channels	2
ADC Resolution	12-bit
Temperature Range	-40°C to +85°C
Power Supply Voltage	1.8 V
Digital Interface	JESD204B
Package	196-Ball BGA