UG-1828 Preliminary Technical Data
Rev. PrB | Page 268 of 277
Figure 261. Automated TDD Configuration Tab
In Figure 248 a sample JSON file with DMR settings has been loaded. The parameters appear in the table for the Rx enable (Rx1 Pin) and
DMA signals. In this example the frame length is 12000000 clock cycles (60ms). Both signals primary assert happens at the beginning of
the frame and then drops on the 6000000 clock cycle (30ms). The frame then repeats itself as the Repeat one frame forever has been
selected.
Enabling Tx1 DMA puts data from FPGA to SSI interface. Disabling Tx1 DMA stops putting data from FPGA to SSI interface. It works
together with Tx_interface enbling/disabling (accepting data from SSI at Navassa) so it provides more flexibility for user to control what
data to transmit. For example, we can have 4 different scenarios:
• DMA disabled, Tx_interface disabled: nothing is transmitted
• DMA disabled, Tx_interface enabled: 0s are transmitted
• DMA enabled, Tx_interface disabled: Data in DMA are not transmitted and it is lost
• DMA enabled, Tx_interface enabled: Data in DMA are transmitted
The Tx1 DMA trigger is defined by the following enum:
typedef enum adi_fpga9001_DmaTrigger
{
ADI_FPGA9001_DMA_TRIGGER_SMA_1 = 0,
ADI_FPGA9001_DMA_TRIGGER_SMA_2 = 1,
To Next Page
Loading...