Analog Devices ADRV9002

Preliminary Technical Data UG-1828
Rev. PrB | Page 69 of 277
Note the minimum guard time discussed above does not consider the time takes to power down transmit or receive analog by assuming
it is insignificant. But it is highly recommended to allow extra time to make sure analog power up happens only after analog power down
is fully completed. The analog power down time is usually much less than the analog power up time.
PIN: CH_ENABLE
CH ANALOG
POWER SAVINGS MODE 2
POWER SAVINGS MODE 1
POWER SAVINGS MODE 0
LDO POWER UP / DOWN
PLL POWER UP / DOWN
PLL TUNING
t
PowerUpPSM2
t
PowerDnPSM2
t
PowerDnPSM1
t
chEnaRise2AnaOn
t
chEnaSetup
t
chEnaFall2Off
IDLE
Tx CHANNEL ANALOG POWER UP / DOWN
t
PowerUpPSM1
24159-064
Figure 63. Channel Power-Up and Power-Down Sequences in Different Power Savings Modes
Figure 63 shows the sequence of events taken to power up or power down a transmit or receive channel in the various channel power
savings modes. It can be seen in Power Savings Mode 1 and Power Savings Mode 2, the enableRiseToAnalogOnDelay is used to power
up additional entities that may have been powered down at the end of the previous frame. (Note in Power Savings Mode 1 and Power
Savings Mode 2, PLL is powered down at the end of the previous frame. Therefore, when it is turned on at the start of the new frame, PLL
tuning is required.) Thus, the enableRiseToAnalogOnDelay must be set long enough to allow these power up procedures to complete. If
the additional power-up procedures in Power Savings Mode 2 takes t
PowerUpPSM2
to complete, the ADRV9001 prevents the system from
entering Power Savings Mode 2, unless enableRiseToAnalogOnDelay is set greater than t
PowerUpPSM2
. Refer to the Impact of Power Savings
on Timing Parameter Selection section for more details on hardware and software restrictions. Similarly, the same is true for Power
Savings Mode 1, the ADRV9001 prevents the system from entering Power Savings Mode 1, unless enableRiseToAnalogOnDelay is set
greater than t
PowerUpPSM1
. In Power Savings Mode 0, which is the default mode, there are no additional power up procedures, thus there are
no additional restrictions on enableRiseToAnalogOnDelay other than those already specified in earlier sections.
If switching dynamically between several power savings modes, user should set the enableRiseToAnalogOnDelay to satisfy the
restrictions of the highest power savings mode. Figure 63 shows that there is a longer idle time when switching to a lower power savings
mode. The parameter enableRiseToAnalogOnDelay cannot be changed dynamically, thus the timing of the TX_ENABLE/RX_ENABLE
rising edge relative to the on air time should also remain the same even when dynamically switching between different power savings
modes.
In certain use cases, when transmit and receive are using the same LO but at different frequencies, if the transition times between
transmit and receive frames are always long enough, PLL tuning is performed at the start of the frame. This is not related to any specific
power saving mode and PLL tuning happens even in Power Saving Mode 0. The timing diagram looks like Figure 64.
PIN: CH_ENABLE
CH ANALOG
POWER SAVINGS MODE 2
POWER SAVINGS MODE 1
POWER SAVINGS MODE 0
LDO POWER UP / DOWN
PLL POWER UP / DOWN
PLL TUNING
t
PowerUpPSM2
t
PowerDnPSM2
t
PowerDnPSM1
t
chEnaRise2AnaOn
t
chEnaFall2Off
IDLE
Tx CHANNEL ANALOG POWER UP / DOWN
t
PowerUpPSM1
t
chEnaSetup
24159-065
Figure 64. Channel Power-Up and Power-Down Sequence in Different Power Savings Modes (PLL Retune @ Frame Boundary Case)