GR740-UM-DS, Nov 2017, Version 1.7 105 www.cobham.com/gaisler
GR740
10.5.3 Data transfers
There is no extra time penalty in the case data is corrected compared to the error-free case.
Only writes of 64 bit width or higher will translate directly into write cycles to the external memory.
Other types of write accesses will generate a read-modify-write (RMW) cycle in order to correctly
update the check-bits. In the special case where an uncorrectable error is detected while performing
the RMW cycle, the write is aborted and the incorrect checkbits are left unchanged so they will be
detected upon the next read.
10.5.4 Configuration
Checkbits are always generated when writing even if EDEN is disabled. Which type of code, A or B,
that is used can be controlled by the CODE field in the MUXCFG register. If the code is changed
during operation, you will need to re-initialize the memory to regenerate the check-bits with the new
code. One way to do this is to clear EDEN and then read and rewrite the memory contents.
Code checking on read is disabled on reset and is enabled by setting the EDEN bit in the MUXCFG
register. Before enabling this, the code to be used should be set in the CODE field and the memory
contents should be (re-)initialized.
10.5.5 Diagnostic checkbit access
The checkbits and data can be accessed directly for testing and fault injection. This is done by writing
the address of into the FTDA register. The check-bits and data can then be read and written via the
FTDC and FTDD registers. Note that for checkbits the FTDA address is 64-bit aligned, while for data
it is 32-bit aligned.
When the FTDC or FTDD registers are accessed, the corresponding access to the address configured
in the FTDA register will be performed to the SDRAM and the read data is returned as if it was the
contents of the register. The access will block with wait states until the access has completed, and
unlike regular accesses so also writes will always block.
After the diagnostic data register has been read, the FT control register bits 31:19 can be read out to
see if there were any correctable or uncorrectable errors detected, and where the correctable errors
were located. There is one bit per byte lane describing where any correctable errors occurred. Note
that the location mask is not valid if there were uncorrectable errors.
10.5.6 Code boundary
The code boundary feature allows you to gradually switch the memory from one interleaving mode to
the other and regenerate the checkbits without stopping normal operation. This can be used when
recovering from memory faults, as explained further below.
If the boundary address enable (BAEN) control bit is set, the controller will look at the address of
each access, and use the interleaving mode selected in the CODE field for memory accesses above or
equal to the boundary address, and the opposite code for memory accesses below to the boundary
address.
If the boundary address update (BAUPD) control bit is also set, the controller will shift the boundary
upwards whenever the the address directly above the boundary is written to. Since the written data is
now below the boundary, it will be written using the opposite code. The write can be done with any
size supported by the controller.
10.5.7 Data multiplexing
When code B is used instead of code A, the upper half of the checkbits become unused. The controller
supports switching in this part of the data bus to replace another faulty part of the bus. To do this, one
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