GR740-UM-DS, Nov 2017, Version 1.7 140 www.cobham.com/gaisler
GR740
12.9.12 Diagnostic cache access data registers
Table 141.0xC4 - 0xE0 - DIAGD - Diagnostic cache access data register 0 - 7
12.9.13 Diagnostic cache access tag register
Table 142.0xE4 - DIAGT - Diagnostic cache access tag register
12.9.14 Data RAM error injection register
Table 143.0xE8 - DERRI - Data RAM error injection register
12.9.15 Tag RAM error injection register
Table 144.0xEC - TERRI - Tag RAM error injection register
31 0
CDATAn
NR
rw*
31:0 Cache data word n (CDATAn) - The core has 8 Diagnostic cache access data registers. Diagnostic
cache access data register n holds data bits [31+32*n:32*n] in the cache line.
When using APV protection then the fetched vector is reversed before it is written in the cache. This
means that bit 127 of the fetched vector is located in bit 0 of Diagnostic data access register 0.
* This register can only be accessed if the the STATUS.DE bit is set to 1
31 0
TAG V
NR
rw*
31:1 Cache tag (TAG) - The size of the tag depends on cache size. The contents of the tag depends on
cache size and addressing settings.
0 Valid (V) - Valid bit of tag
* This register can only be accessed if the the STATUS.DE bit is set to 1
31 0
DPERRINJ
0
rw
31:0 Data RAM Parity Error Injection (DPERRINJ) - Bit DPERRINJ[n] in this register is XOR:ed with
the parity bit for data bits [7+8*n:8*n] in the data RAM.
31 0
TPERRINJ
0
rw
31:0 Tag RAM Parity Error Injection (TPERRINJ) - Bit TPERRINJ[n] in this register is XOR:ed with the
parity bit for tag bits [7+8*n:8*n] in the tag RAM.
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