GR740-UM-DS, Nov 2017, Version 1.7 189 www.cobham.com/gaisler
GR740
Table 183. 0x00000984-0x00000930 - RTR.PCTRL2 - Port control 2, ports 1-12 (SpaceWire ports and AMBA ports)
31 24 23 16 15 14 13 12 11 10 9 8 6 5 1 0
SM SV OR UR R AT AR IT IR RESERVED SD SC
0xC0 0x00 1 1 0 1 1 1 1 0x0 0x00 0
rw rw rw rw r rw rw rw rw r rw rw
31: 24 Time-code / distribute interrupt code truncation mask (SM) - Defines which bits of a time-code / distributed
interrupt code that must match the value specified in RTR.PCTRL2.SV in order for a packet, for which this port
is the input port, to be spilled. If a bit in this field is set to 1, the corresponding bit in RTR.PCTRL2.SV must
match the time-code / distribute interrupt code. If a bit in this field is set to 0, the corresponding bit in
RTR.PCTRL2.SV does not have to match the time-code / distributed interrupt code.
23: 16 Time-code / distribute interrupt code truncation value (SV) - Defines the value to use together with the
RTR.PCTRL2.SM field when checking if a time-code / distributed interrupt code should spill a packet for which
this port is the input port.
15 Overrun timeout enable (OR) - Enables spilling due to overrun timeouts for packets for which this port is the
input port. See section 13.2.15 for details.
14 Underrun timeout enable (UR) - Enables spilling due to unerrun timeouts for packets for which this port is the
input port. See section 13.2.15 for details.
13 RESERVED
12 Interrupt acknowledgement code transmit enable (AT) - Enables the transmission of interrupt acknowledgement
codes on this port. If set to 0, no interrupt acknowledgement codes will be forwarded to this port.
11 Interrupt acknowledgement code receive enable (AR) - Enabled the reception of interrupt acknowledgement
codes on this port. If set to 0, all received interrupt acknowledgement codes on this port will be silently dis-
carded.
10 Interrupt code transmit enable (IT) - Enables the transmission of interrupt codes on this port. If set to 0, no inter-
rupt codes will be forwarded to this port.
9 Interrupt code receive enable (IR) - Enabled the reception of interrupt codes on this port. If set to 0, all received
interrupt codes on this port will be silently discarded.
8: 6 RESERVED
5: 1 Static route destination (SD) - When RTR.PCTRL.ST is set to 1, incoming packets on this port will be routed
based on the value of this field, and the setting of RTR.PCTRL2.SC, instead of the packet’s first byte.
0 Static route configuration (SC) - When this bit is set to 1, the RTR.RTPMAP register corresponding to the phys-
ical address specified by the RTR.PCTRL2.SD field will be used when routing packets, if RTR.PCTRL.ST is set
to 1.
Table 184. 0x00000A00 - RTR.RTRCFG - Router configuration / status
31 27 26 22 21 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP AP RESERVED SR PE IC IS IP AI AT IE RE EE R SA TF ME TA PP
0x08 0x04 0x00 1 1 0 0 0 * 1 * 0 * 0 0 * 0 1 1
r r r r r rwrwrwrwrwrwrwrw r rwrwwc r r
31: 27 SpaceWire ports (SP) - Set to the number of SpaceWire ports in the router. Constant value of 0x08.
26: 22 AMBA ports (AP) - Set to the number of AMBA ports in the router. Constant value of 0x04
21: 16 RESERVED
15 Static routing enable (SR) - This read-only bit specifies that the router’s static routing feature is always globally
enabled. See section 13.2.9 for details.
14 SpaceWire Plug-and-Play enable (PE) - This read-only bit specifies that the router’s SpaceWire Plug-and-Play
features are always globally enabled. See section 13.5.4 for details.
13 ISR change timer enable (IC) - If set to 1, the router will wait for the time period specified by the RTR.IRC-
TIMER register after an ISR bit change value, before it allows an incoming interrupt code / interrupt acknowl-
edgement code to change the value of the same ISR bit. If set to 0, the ISR change timers are not used, and an
ISR bit is allowed to change value again as soon as the previous interrupt code / interrupt acknowledgement
code has been distributed.
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