GR740-UM-DS, Nov 2017, Version 1.7 231 www.cobham.com/gaisler
GR740
15.6.3 Data transfer
The DMA engine starts by reading the descriptor for the first DMA channel. If the DMA channel is
enabled the first data descriptor in this channel is read and executed. When the transfer is done the
data descriptor is disabled and status is written to the control word. If no error occurred during the
transfer, the error bit is not set and the transfer length field is unchanged. If the transfer was termi-
nated because of an error, the error bit is set in the control word and the length field indicates where in
the transfer the error occurred. If no error has occurred, the next data descriptor is read and executed.
When a disabled data descriptor is read or the maximum number of data descriptors has been exe-
cuted, the DMA channel descriptor is updated to point to the next data descriptor and the DMA engine
moves on to the next DMA channel.
When a disabled channel descriptor is read, the DMA controller will move on to the next DMA chan-
nel without reading any data descriptors from the disabled channel (only applies to silicon revision 1,
see section 43).
When the DMA is disabled (via the APB interface), the channel descriptor is updated to point to the
next data descriptor (only applies to silicon revision 1, see section 43).
The DMA engine will stop when an error is detected or when no enabled data descriptors is found.
The error type is indicated by bit 7 to bit 11 in the DMA control register. The error type bits must be
cleared (by writing ‘1’) before the DMA can be re-enabled.
15.6.4 Interrupt
The DMA controller has a interrupt enable bit in the DMA control register (accessible via the APB
slave interface) which enables interrupt generation.
Each data descriptor has an interrupt enable bit which determine if the core should generate a interrupt
when the descriptor has been executed.
The DMA engine asserts the same interrupt as the PCI core.
Table 269. GRPCI2 DMA data control
31 30 29 28 22 21 20 19 18 16 15 0
EN IE DR BE RESERVED Type ER RESERVED LEN
31 Data descriptor enable.
30 Interrupt generation enable.
29 Transfer direction. 0: PCI to AMBA, 1: AMBA to PCI.
28 PCI bus endianess switch. 1: defines the PCI bus to be little-endian for this transfer, 0: defines the
PCI bus to be big-endian for this transfer.
27: 22 RESERVED (Must be set to zero)
21: 20 Descriptor type. 00 = DMA data descriptor.
19 Error status
18: 16 RESERVED
15: 0 Transfer length. The number of word of the transfer is (this field)+1.
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