GR740-UM-DS, Nov 2017, Version 1.7 314 www.cobham.com/gaisler
GR740
21.3.19 Processor boot register
Note: This register is only present in GR740 silicon revision 0.
Table 398.0x240 - PBOOT - Processor boot register
31 20 19 16 15 4 3 0
RESERVED RESET[n] RESERVED BOOT[n]
0000
rrw*rrw*
31: 20
RESERVED
19: 16
Processor reset (RESET): Writing bit n of this field to ‘1’ will reset, but not start, processor n. When
the processor has been reset the bit will be reset to ‘0’. A processor can only be reset if it is currently
idle (in power-down, error or debug mode), if a processor is running then the write to its bit in this
field will be ignored. Multiple bits in this register may be set with one write but the register can only
be written when all bits are zero.
15: 4
RESERVED
3: 0
Processor boot (BOOT): Writing bit n of this field to ‘1’ will reset and start processor n. When the
processor has been booted the bit will be reset to ‘0’. A processor can only be started if it is currently
idle (in power-down, error or debug mode), if a processor is running then the write to its bit in this
field will be ignored. Multiple bits in this register may be set with one write but the register can only
be written when all bits are zero.
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