COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 368 www.cobham.com/gaisler
GR740
Wire Time-Code) but no new time message is received (NC bit is zero). When the local ET counter is
initialized or synchronized the NC bit in the control register will disable itself. The INSYNC bit in
Status 0 register will enable when initialization is performed specifying the target is initialized. Initial-
ization completely writes time message values into the implemented local Elapsed time counter and
synchronisation verifies whether the time message Command Elapsed Time and local Elapsed Time
counter matches till the mapped SpaceWire Time-Code level (with a tolerance of previous value) and
only modifies the local Elapsed Time if their is a mismatch. If the target is not implemented with jitter
and mitigation unit then the synchronisation forces the target time (ET counter) with the time message
received.
For example, the initiator can create time message exactly at 0x00000001 coarse time and 0x040000
fine time (32 bit coarse time and 24 bit fine time, mapping value of 6 i.e. 64 SpaceWire Time-Codes
per second, time message is generated at 0b000001 SpaceWire Time-Code), the value in the time
message to be sent to the target can be coarse time 0x00000002 and 0x040000 fine time, (32 bit
coarse time and 24 bit fine time, mapping value of 6, time message is qualified at the next reception of
0b000001 SpaceWire Time-Code, i.e. after a second). Both SPWTC in Control registers available in
the initiator and target can be 0b000001 for this example. The time is synchronized after a second in
this example. Depending on the frequency of SpaceWire Time-Codes and data link rate several differ-
ent combination of ways to achieve time synchronisation is possible.
31.3.9 Latency measurement using Time-Stamps
The incoming and outgoing SpaceWire Distributed Interrupts are time stamped in initiator and target.
The initiator calculates latency based on these time stamp values. The time stamped values in target
are accessed from initiator through RMAP. The Latency Enable LE bit in Configuration 0 register
must be enabled between the two nodes in the SpaceWire network for which the latency is to be calcu-
lated. The core supports 32 distributed interrupts and acknowledgment (Interrupt and acknowledg-
ment numbers 0 to 31) or 64 distributed interrupts (only in silicon revision 1). The distributed
interrupt transmission from initiator (which is the origin for latency calculation) is controlled by a
mask register STM available in Configuration 3 register and SpaceWire time code register TSTC
available in Time-Stamp SpaceWire Time-Code and Preamble Field Tx register, these registers speci-
fies how often and at which time code distributed interrupt is transmitted and time stamping is per-
formed.
The time stamping can be performed in two methods (only Interrupts or Interrupts and Acknowledg-
ment), the DI bit in Configuration 3 register of SPWTDP component in target should be configured to
specify which type of method is used. If only distributed interrupts (no acknowledgment) are used
then DI bit should be 0. The transmitted and received distributed interrupts INTX and INRX in the
Configuration 0 registers of both initiator and target must be configured with the interrupt number
which will be used for the latency measurement. For example if the INTX in initiator Configuration 0
is configured with 0b00100 then the target INRX should be configured with the same value. Similarly
if the INTX in target Configuration 0 is configured to be 0b00101 then the initiator INRX should be
configured with the same value. Initially initiator sends a distributed interrupt when the conditions are
matched (STM and TSTC registers match) and when the target received this distributed interrupt it
will send another interrupt which will be received by the initiator. At each end transmission and recep-
tion is time stamped (current local time is stored in Time Stamp registers) and interrupt transmitted is
INTX and received interrupt is checked whether it received INRX.
If both distributed interrupts and acknowledgment method is to be used then DI bit should be 1. The
transmitted and received distributed interrupts INTX and INRX in the Configuration 0 registers of
both initiator and target can have the same interrupt number (the acknowledgment number for a par-
ticular interrupt will be same as interrupt number). Similar to the previous method at each end trans-
mission and reception is time stamped which will be used for latency calculations.
The Latency calculation can be started in initiator based on DIR (distributed interrupt received) inter-
rupt available in Interrupt Status register (the interrupt should be enabled in the Interrupt Enable regis-
ter). The latency is calculated form the time stamp registers based on the equation explained below

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English