GR740-UM-DS, Nov 2017, Version 1.7 369 www.cobham.com/gaisler
GR740
Latency = ((initiator time stamp Rx - initiator time stamp Tx) - (target time stamp Tx - target time
stamp Rx)) /2
By calculating the Latency value repeatedly (at least for about 128 times, more number of times pro-
vides increased accuracy) and taking an average of it will provide the final latency value. The initiator
should transfer the latency correction information to the Latency Field registers in the target by means
of RMAP transfer. When the latency values are written it will be adjusted to local time in the target
and the LC bit in Status 0 register is enabled (set to ‘1’), this status register can be disabled by writing
‘1’ into the corresponding field.
31.3.10 External Datation
The core provides external datation services, there are four external datation services implemented
which can time stamp the Elapsed Time counter when the conditions for a respective event (time
stamping) occurs. The event on which time stamp must occur is configurable individually (using the
respective mask registers EDMx and also a dedicated mask bit is available for each of the input
events) for all the external datation services.
Each of the four external datation services implemented has its own mask EDMx, status EDS and
time EDxETx registers. (here the x suffix represent 0, 1, 2 and 3 respect to individual registers avail-
able)
All the external datation services share the same event inputs (32 inputs).
The table be
low describes the inputs connected.
Any condition match for a particular external datation service will clear its respective mask register
EDMx (clears all the mask bits and must be set again inorder to achieve an another time stamp). An
output pulse is also produced when conditions are met (respective TDP controller datation pulse out-
put is driven high for a clock period). The EDS bit in Status Register 0 will go high when the condi-
tion matches and cleared when the latched elapsed time is read. The purpose of this status register is to
ensure that all the implemented coarse and fine time are read. Reading the lowest implemented fine
time makes the status register to go low.
31.3.11 Set Elapsed Time using external input
Note: This functionality is only available in silicon revision 1.
The ET counter can be set using an external enable signal (configurable rising or falling edge, see reg-
ister SP in Configuration 0 register). To set the ET counter the SE bit in configuration register must be
Table 467. Input Events on which time stamp occurs.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
irq
31
irq
30
irq
29
irq
28
irq
27
irq
26
irq
25
irq
24
irq
23
irq
22
irq
21
irq
20
irq
19
irq
18
irq
17
irq
16
irq
15
irq
14
irq
13
irq
12
irq
11
LS irq
9
irq
8
irq
7
irq
6
irq
5
irq
4
irq
3
irq
2
irq
1
irq
0
31: 11 The Interrupt lines (11 to 31) are connected as input events. The respective mask bit must be enabled
to time stamp on this event and when the condition matches (Interrupt occurs) the time stamp values
are available in respective EDxETx registers.
10 Latch-Save (LS) : Input 10 is special case.
MIL-STD-1553B controller RTSYNC event.
The Elapsed Time is continuously latched when a valid command is detected by the controller (the
corresponding mask register bit 10 must be enabled).
When RTSYNC event is reported by the MIL-STD-1553B controller the latched value will remain
same (saved at when the previous latch condition met) and all the mask bit previously enabled will
be cleared. The RTSYNC event is necessary to finalize the condition match.
9: 0 The Interrupt lines (0 to 9) are connected as input events. The respective mask bit must be enabled to
time stamp on this event and when the condition matches (Interrupt occurs) the time stamp values
are available in respective EDxETx registers.
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