GR740-UM-DS, Nov 2017, Version 1.7 404 www.cobham.com/gaisler
GR740
33.6.15 Instruction trace buffer control register 0
The instruction trace control register contains filter configuration and a pointer that indicates the next
line of the instruction trace buffer to be written.
33.6.16 Instruction trace buffer control register 1
The instruction trace control register 1 contains settings used for trace buffer overflow detection. This
register can be written while the processor is running.
Table 540. 0x110000 - ITBC0 - Instruction trace buffer control register 0
31 28 27 98 0
TFILT RESERVED ITPOINTER
00 NR
rw r rw
31: 28 Trace filter configuration (TFILT) - See table 522.
27: 9 RESERVED
15: 0 Instruction trace buffer pointer (ITPOINTER) - Indicates the next line of the instruction trace buffer
to be written
Table 541. 0x110004 - ITBC1 - Instruction trace buffer control register 1
31 28 27 26 24 23 22 0
RESERVED W
O
TLIM T
O
V
RESERVED
0 000 0
r rwrwrw r
31: 28 RESERVED
27 Watchpoint on overflow (WO) - If this bit is set, and Break on iu watchpoint (BW) is enabled in the
DSU control register, then a watchpoint will be inserted when a trace overflow is detected (TOV
field in this register gets set).
26: 24 Trace Limit (TLIM) - TLIM is compared with the top bits of ITBC0.ITPOINTER to generate the
value in the TOV field below.
23 Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of
ITPOINTER.
22: 0 RESERVED
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