GR740-UM-DS, Nov 2017, Version 1.7 434 www.cobham.com/gaisler
GR740
36.3.6 Trace buffer breakpoint registers
The trace buffer contains two breakpoint registers for matching AHB addresses. A breakpoint hit is
used to freeze the trace buffer by clearing the enable bit. Freezing can be delayed by programming the
DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT value will
be decremented for each additional trace until it reaches zero and after two additional entries, the trace
buffer is frozen. A mask register is associated with each breakpoint, allowing breaking on a block of
addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during break-
point detection. To break on AHB load or store accesses, the LD and/or ST bits should be set.
Table 571. 0x000010, 0x000018 - TBBA - Trace buffer break address registers
31 210
BADDR[31:2] RES
NR 0
rw r
31: 2 Break point address (BADDR) - Bits 31:2 of breakpoint address
10 RESERVED
Table 572. 0x000014, 0x00001C - TBBM - Trace buffer break mask registers
31 210
BMASK[31:2] LD ST
NR 0 0
rw rw rw
31: 2 Breakpoint mask (BMASK) - See description above tables.
1 Load (LD) - Break on data load address
0 Store (ST) - Break on data store address
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