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GR740-UM-DS, Nov 2017, Version 1.7 476 www.cobham.com/gaisler

GR740

40.4.3 Package drawing for GR740-[YY,CP,MP,MSEQ,MSEV,MSQ,MSV]-LG625

Table of Contents

Default Chapter2
- Table of Contents2
1 Introduction8
- Scope8
- Preliminary Data Sheet Limitations8
- Updates and Feedback8
- Software Support8
- Development Board8
- Performance, Power Consumption and Radiation Tolerance8
- Reference Documents9
- Document Revision History10
- Acronyms13
- Definitions14
- Register Descriptions15
2 Architecture16
- Overview16
- Cores18
- Memory Map19
- Interrupts22
- Plug & Play and Bus Index Information22
3 Signals27
- Bootstrap Signals27
- Configuration for Flight28
- Pin Multiplexing28
- Complete Signal List32
- Pin Driver Configuration35
4 Clocking and Reset36
- Clock Inputs36
- Clock Loop for SDRAM36
- Reset Scheme37
- Clock Multiplexing for Main System Clock, SDRAM and Spacewire38
- PLL Control and Configuration39
- PLL Watchdog40
- PCI Clock40
- MIL-STD-1553B Clock40
- Clock Gating Unit40
- Debug AHB Bus Clocking41
- Notes on Ethernet Interface Clock and Mode Switch41
5 Technical Notes42
- GRLIB AMBA Plug&Play Scanning42
- Processor Register File Initialisation and Data Scrubbing42
- PROM-Less Systems and Spacewire RMAP42
- System Integrity and Debug Communication Links43
- Separation and ASMP Configurations43
- Clock Gating44
- Software Portability45
- Level-2 Cache45
- Time Synchronisation46
- Bridges, Posted-Writes and ERROR Response Propagation47
6 LEON4 - Fault-Tolerant High-Performance SPARC V8 32-Bit Processor48
- Overview48
- LEON4 Integer Unit50
- Cache System56
- Memory Management Unit59
- Floating-Point Unit60
- Co-Processor Interface61
- AMBA Interface61
- Multi-Processor System Support63
- ASI Assignments64
- Configuration Registers69
- Software Considerations78
7 Floating-Point Control Unit80
- Floating-Point Register File80
- Floating-Point State Register (FSR)80
- Floating-Point Exceptions and Floating-Point Deferred-Queue80
8 High-Performance IEEE-754 Floating-Point Unit82
- Overview82
- Functional Description82
9 Level 2 Cache Controller86
- Overview86
- Operation86
- Operation89
- Registers92
10 SDRAM Memory Controller with Reed-Solomon EDAC100
- Overview100
- Operation100
- Limitations100
- SDRAM Back-End Operation101
- Fault-Tolerant Operation104
- Registers107
- Sdram Configuration Register108
11 Memory Scrubber and AHB Status Register112
- Overview112
- Operation112
- Registers115
- Configuration Register118
12 IOMMU - Bridge Connecting Master I/O AHB Bus121
- Overview121
- Bridge Operation121
- General Access Protection and Address Translation124
- Access Protection Vector125
- IO Memory Management Unit (IOMMU) Functionality127
- Fault-Tolerance130
- Statistics131
- ASMP Support131
- Registers132
- Interrupt Mask Register137
13 Spacewire Router142
- Overview142
- Operation142
- Spacewire Ports152
- AMBA Ports154
- Configuration Port177
14 Gigabit Ethernet Media Access Controller (MAC)204
- Overview204
- Operation204
- Tx DMA Interface205
- Rx DMA Interface207
- MDIO Interface210
- Ethernet Debug Communication Link (EDCL)210
- Media Independent Interfaces212
- Registers213
32 Bit PCI/AHB Bridge218
- Overview218
- Configuration218
- Operation224
- PCI Initiator Interface227
- PCI Target Interface228
- DMA Controller229
- PCI Trace Buffer232
- Interrupts232
- Reset233
- 15.10 Registers233
16 MIL-STD-1553B / AS15531 Interface241
- Overview241
- Electrical Interface241
- Operation242
- Bus Controller Operation243
- Remote Terminal Operation248
- Event Log250
- Bus Monitor Operation252
- Clocking and Reset252
- Registers253
17 CAN 2.0 Controllers with DMA263
- Overview263
- Interface264
- Protocol264
- Status and Monitoring264
- Transmission264
- Reception267
- Global Reset and Enable270
- Interrupt270
- Registers271
- 17.10 Memory Mapping281
18 Bridge Connecting Slave I/O AHB Bus to Processor AHB Bus282
- Overview282
- Operation282
- Registers285
19 Fault-Tolerant 8/16-Bit PROM/IO Memory Interface286
- Overview286
- PROM Access286
- Memory Mapped IO288
- 8-Bit and 16-Bit PROM Access289
- 8- and 16-Bit I/O Access290
- Burst Cycles290
- Memory EDAC291
- Bus Ready Signalling291
- Registers293
20 General Purpose Timer Units297
- Overview297
- Operation297
- Registers298
21 Multiprocessor Interrupt Controller with Extended ASMP Support301
- Overview301
- Operation301
- Registers306
22 General Purpose I/O Ports316
- Overview316
- Operation316
- Registers317
23 UART Serial Interfaces323
- Overview323
- Operation323
- Baud-Rate Generation324
- Loop Back Mode325
- FIFO Debug Mode325
- Interrupt Generation325
- Registers326
24 SPI Controller Supporting Master and Slave Operation328
- Overview328
- Operation328
- Registers331
25 Clock Gating Unit338
- Overview338
- Operation338
- Registers339
26 LEON4 Statistics Unit (Performance Counters)342
- Overview342
- Multiple APB Interfaces344
- Registers345
27 AHB Status Registers349
- Overview349
- Operation349
- Registers350
28 Register for Bootstrap Signals351
- Overview351
- Operation351
- Registers351
29 Temperature Sensor Controller353
- Overview353
- Operation353
- Registers354
30 Register Bank for I/O and PLL Configuration Registers356
- Overview356
- Operation356
- Registers358
31 Spacewire - Time Distribution Protocol Controller363
- Overview363
- Protocol363
- Functionality363
- Registers370
32 Bridge Connecting Debug AHB Bus to Processor AHB Bus385
- Overview385
- Operation385
- Registers388
33 LEON4 Hardware Debug Support Unit389
- Overview389
- Operation389
- AHB Trace Buffer390
- Instruction Trace Buffer392
- DSU Memory Map393
- DSU Registers395
34 JTAG Debug Link with AHB Master Interface405
- Overview405
- Operation405
- Registers406
35 Spacewire Debug Link407
- 35.2.1 Overview407
- Operation407
- Link Interface408
- Time-Code Distribution410
- Receiver DMA Channels410
- Transmitter DMA Channels415
- Rmap418
- AMBA Interface422
- Registers423
36 AHB Trace Buffer Tracing Master I/O AHB Bus429
- Overview429
- Operation429
- Registers431
37 AMBA AHB Controller with Plug&Play Support435
- Overview435
- Operation435
38 AMBA AHB/APB Bridge with Plug&Play Support437
- Overview437
- Operation437
39 Electrical Description438
- Absolute Maximum Ratings438
- Recommended DC Operating Conditions438
- Input and Output Signal DC Characteristics439
- Power Supplies439
- AC Characteristics441
40 Mechanical Description458
- Component and Package458
- Package Placement Diagram459
- Pin Assignment460
- Package Drawing475
41 Temperature and Thermal Resistance479
42 Ordering Information480
43 Silicon Revisions and Errata481
- Overview481
- Change and Errata Descriptions482

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