COBHAM GR740 - Page 5

GR740-UM-DS, Nov 2017, Version 1.7 5 www.cobham.com/gaisler
GR740
19 Fault-tolerant 8/16-bit PROM/IO Memory Interface .......................................................... 286
19.1 Overview ............................................................................................................................................. 286
19.2 PROM access ...................................................................................................................................... 286
19.3 Memory mapped IO ............................................................................................................................ 288
19.4 8-bit and 16-bit PROM access............................................................................................................. 289
19.5 8- and 16-bit I/O access....................................................................................................................... 290
19.6 Burst cycles ......................................................................................................................................... 290
19.7 Memory EDAC ................................................................................................................................... 291
19.8 Bus Ready signalling........................................................................................................................... 291
19.9 Registers .............................................................................................................................................. 293
20 General Purpose Timer Units............................................................................................... 297
20.1 Overview ............................................................................................................................................. 297
20.2 Operation ............................................................................................................................................. 297
20.3 Registers .............................................................................................................................................. 298
21 Multiprocessor Interrupt Controller with extended ASMP support..................................... 301
21.1 Overview ............................................................................................................................................. 301
21.2 Operation ............................................................................................................................................. 301
21.3 Registers .............................................................................................................................................. 306
22 General Purpose I/O Ports ................................................................................................... 316
22.1 Overview ............................................................................................................................................. 316
22.2 Operation ............................................................................................................................................. 316
22.3 Registers .............................................................................................................................................. 317
23 UART Serial Interfaces........................................................................................................ 323
23.1 Overview ............................................................................................................................................. 323
23.2 Operation ............................................................................................................................................. 323
23.3 Baud-rate generation ........................................................................................................................... 324
23.4 Loop back mode .................................................................................................................................. 325
23.5 FIFO debug mode................................................................................................................................ 325
23.6 Interrupt generation ............................................................................................................................. 325
23.7 Registers .............................................................................................................................................. 326
24 SPI Controller supporting master and slave operation ........................................................ 328
24.1 Overview ............................................................................................................................................. 328
24.2 Operation ............................................................................................................................................. 328
24.3 Registers .............................................................................................................................................. 331
25 Clock gating unit.................................................................................................................. 338
25.1 Overview ............................................................................................................................................. 338
25.2 Operation ............................................................................................................................................. 338
25.3 Registers .............................................................................................................................................. 339
26 LEON4 Statistics Unit (Performance Counters).................................................................. 342
26.1 Overview ............................................................................................................................................. 342
26.2 Multiple APB interfaces ......................................................................................................................344
26.3 Registers .............................................................................................................................................. 345
27 AHB Status Registers .......................................................................................................... 349
27.1 Overview ............................................................................................................................................. 349
27.2 Operation ............................................................................................................................................. 349
27.3 Registers .............................................................................................................................................. 350