COBHAM GR740 - Page 6

GR740-UM-DS, Nov 2017, Version 1.7 6 www.cobham.com/gaisler
GR740
28 Register for bootstrap signals............................................................................................... 351
28.1 Overview ............................................................................................................................................. 351
28.2 Operation ............................................................................................................................................. 351
28.3 Registers .............................................................................................................................................. 351
29 Temperature sensor controller.............................................................................................. 353
29.1 Overview ............................................................................................................................................. 353
29.2 Operation ............................................................................................................................................. 353
29.3 Registers .............................................................................................................................................. 354
30 Register Bank For I/O and PLL configuration registers ...................................................... 356
30.1 Overview ............................................................................................................................................. 356
30.2 Operation ............................................................................................................................................. 356
30.3 Registers .............................................................................................................................................. 358
31 SpaceWire - Time Distribution Protocol Controller ............................................................ 363
31.1 Overview ............................................................................................................................................. 363
31.2 Protocol ...............................................................................................................................................363
31.3 Functionality........................................................................................................................................ 363
31.4 Registers .............................................................................................................................................. 370
32 Bridge connecting Debug AHB bus to Processor AHB bus ................................................ 385
32.1 Overview ............................................................................................................................................. 385
32.2 Operation ............................................................................................................................................. 385
32.3 Registers .............................................................................................................................................. 388
33 LEON4 Hardware Debug Support Unit............................................................................... 389
33.1 Overview ............................................................................................................................................. 389
33.2 Operation ............................................................................................................................................. 389
33.3 AHB Trace Buffer ............................................................................................................................... 390
33.4 Instruction trace buffer ........................................................................................................................ 392
33.5 DSU memory map............................................................................................................................... 393
33.6 DSU registers ......................................................................................................................................395
34 JTAG Debug Link with AHB Master Interface ................................................................... 405
34.1 Overview ............................................................................................................................................. 405
34.2 Operation ............................................................................................................................................. 405
34.3 Registers .............................................................................................................................................. 406
35 SpaceWire Debug Link ........................................................................................................ 407
35.1 Overview ............................................................................................................................................. 407
35.2 Operation ............................................................................................................................................. 407
35.3 Link interface ...................................................................................................................................... 408
35.4 Time-Code distribution ....................................................................................................................... 410
35.5 Receiver DMA channels...................................................................................................................... 410
35.6 Transmitter DMA channels ................................................................................................................. 415
35.7 RMAP.................................................................................................................................................. 418
35.8 AMBA interface .................................................................................................................................. 422
35.9 Registers .............................................................................................................................................. 423
36 AHB Trace buffer tracing Master I/O AHB bus .................................................................. 429
36.1 Overview ............................................................................................................................................. 429
36.2 Operation ............................................................................................................................................. 429
36.3 Registers .............................................................................................................................................. 431