GR740-UM-DS, Nov 2017, Version 1.7 65 www.cobham.com/gaisler
GR740
The processor implements SPARC V8E nonprivileged ASI access, accesses to ASI 0x80 - 0xFF do
not require supervisor privileges. No registers are mapped at ASI 0x80 - 0xFF and the instructions
used to access these areas can be used as trace points for software tracing. Trace filtering (see section
33.4) allows filtering of these instructions.
6.9.2 ASI 0x1, Forced cache miss
ASI 1 is used for systems without cache coherency, to load data that may have changed in the back-
ground, for example by DMA units. It can also be used for other reasons, for example diagnostic pur-
poses, to force a AHB load from memory regardless of cache state.
The address mapping of this ASI is matched with the regular address space, and if MMU is enabled
then the address will be translated normally. Stores to this ASI will perform the same way as ordinary
data stores.
For situations where you want to guarantee that the cache is not modified by the access, the MMU and
cache bypass ASI, 0x1C, can be used instead. However this is only available when MMU is imple-
mented.
To Next Page
Loading...
Need help?
General
