GR740-UM-DS, Nov 2017, Version 1.7 91 www.cobham.com/gaisler
GR740
by writing an address together with the inject bit to the “Error injection” register. This will XOR the
check-bits for the specified address with the data-check-bit register. If the specified address in not
cached, the cache contents will be unchanged.
9.3.7 AHB slave interface
The cache can accept 8-bit (byte), 16-bit (half word), 32-bit (word), 64-bit, and 128-bit single
accesses and also 32-bit, 64-bit, and 128-bit burst accesses. For an access during a flush operation, the
cache will respond with an AHB SPLIT response or with wait-states. For an uncorrectable error or a
backend AHB error on a read access, the cache will respond with an AMBA ERROR response. For a
correctable data error which require a cache line to be re-fetched from memory the cache will respond
with a AMBA RETRY response.
9.3.8 AHB master interface
The master interface is the cache’s connection to the memory controller. During cache line fetch, the
controller can issue either a 32-bit, 64-bit or 128-bit burst access. For a non cachable access and in
write-through mode the cache can also issue a 8-bit (byte), 16-bit (half word), 32-bit (word), 64-bit, or
128-bit single write access.
9.3.9 Cache status
The cache controller has a status register that provides information on the cache configuration (multi-
way configuration and set size). The cache also provides access, hit and error correction counters via
the LEON4 statistics unit (see section 26).
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