Section
IV
the de offset voltage to select any I 0
dB
portion
of
the
80
dB
range. The
output
of
the Video Output Circuit,
ranging from 0 V to + 5 V de,
is
applied to the rear panel
Y-AXIS output connector and to the Digital Storage
Section.
4-16.
Frequency
and
Sweep
Section.
4-17.
The
Frequency and Sweep Section consists basically
of
a Ramp Generator, a Dial Mixing Amplifier, a Voltage-
Tuned Local Oscillator (VTO) and a Tracking Oscillator.
4-18.
Ramp
Generator. The Ramp Generator produces a
0 V to
+5
V linear ramp which
is
applied to the
Dial
Mixing
Amplifier and to the Digital Storage Section. The frequency
of
the ramp
is
determined by the front panel
SWEEP
TIME
setting. The FREQ
SPAN
control, located between the
Ramp Generator and
Dial
Mixing Amplifier, determines the
amplitude
of
the ramp applied to the VTO and thus, the
overall change in frequency produced by the ramp.
4-19. Dial Mixing Amplifier. In the
Dial
Mixing
Amplifier,
the ramp voltage
is
combined with a variable
de
voltage
from the front panel FREQUENCY control. This
de
voltage
establishes the low-frequency limit or "start frequency"
of
the VTO.
4-20. VTO. The VTO generates a I 00 kHz to 150 kHz
square
wave
which
is
applied to the Input Mixer in the
Amplitude Section and
to
the Tracking Oscillator.
4-21.
Tracking
Oscillator.
In the Tracking Oscillator, the
100 kHz to 150 kHz VTO signal
is
mixed with a I 00 kHz
signal
from a crystal oscillator. This produces the 0
Hz
to
50 kHz tracking signal which
is
available
at
the rear panel
TRACKING
OSC
OUT
connector.
4-22.
Digital
Storage
Section.
4-23. Because
of
the extremely slow sweep rates used in
the 3580A, some form
of
display storage
is
required. The
most common method for obtaining display storage
is
to
use a storage CRT in which the display
is
retained by the
phosphor or by a "storage mesh" located behind the CRT
face. Relatively recent advances
in
large-scale integrated
circuits, however, have made it possible to
use
a digital
storage technique
in
the 3580A. Digital storage permits the
use
of
a standard oscilloscope CRT and further provides
several operating conveniences not available with conven-
tional displays.
4-24. In the Digital Storage Section, the 0 V
to
+ 5 V
"frequency ramp" from the Frequency and Sweep Section
is
applied to an A to D converter where it
is
converted to
binary and used to address a memory bank. At the
same
time, the detected video information from the Amplitude
Section
is
converted to binary by
an
A to D converter and
stored in the memory locations addressed by the ramp. The
binary video data
is
then non-destructively read
out
of
memory, converted
to
de, processed and applied to the
vertical deflection plates
of
the CRT.
4-2
Model 3580A
4-25. During the read cycle, a "display ramp," generated in
the Digital Storage Section,
is
used to address the memory
and drive the horizontal deflection plates
of
the CRT. The
display ramp scans the memory and sweeps the display
approximately 50 times each second. This is a much faster
rate than that
of
the frequency ramp used for storing data.
The memory contents are, therefore, refreshed at the slow
frequency-sweep rate, while data
is
read-out
of
memory at
the rapid display-sweep rate. The result
is
a flicker-free,
stored presentation.
4-26.
When
the front panel STORE button
is
pressed, the
display currently in memory
is
processed and stored in
one-half
of
the memory locations. This
leaves
the other half
of
the memory available for the refresh trace. During the
read cycle, the display ramp first scans the memory
locations containing the refresh trace.
It
then recycles and
scans the locations containing the previously stored trace.
Due
to the rapid scan rate
of
the display ramp, the stored
trace and the refresh trace appear simultaneously
on
·the
CRT.
4-27.
FUNCTIONAL
DESCRIPTION.
4-28.
Amplitude
Section.
4-29. Refer to the Amplitude Section Detailed Block
Diagram (Figure 7-3) for the following discussion.
4-30. Input Attenuator. The Input Attenuator, controlled
by the front panel INPUT SENSITIVITY switch,
serves
as
an
input voltage divider and coupling network between the
INPUT connector and the Input Amplifier.
The
attenuator
is
comprised
of
5 R/C divider networks. These networks
provide the required signal attenuation for the +30
dB
(20 V) through - 10
dB
(0.2 V) ranges.
On
the - 20
dB
(0.1 V) through - 70
dB
(0.2 mV) ranges, the Input Attenu-
ator
is
bypassed by the Input Sensitivity switch and the
input
signal
is
applied directly to the Input Amplifier. Table
1
of
the Detailed Block Diagram lists the maximum (full
scale) input levels, input attenuation and resulting
signal
levels applied to the Input Amplifier for each INPUT
SENSITIVITY setting.
4-31. Input Amplifier. The Input Amplifier
is
a low noise,
high input-impedance amplifier circuit which provides
variable gain and impedance conversion between the Input
Attenuator and the Post Attenuator. The Input Amplifier
gain, controlled by the INPUT SENSITIVITY switch,
is
approximately Xl.25 ( + 1.8
dB)
on the + 30
dB
through
- 50
dB
ranges and
is
increased to
Xl
2.5 (+21.8 dB) on the
- 60
dB
and - 70
dB
ranges. Table 1
of
the Detailed Block
Diagram lists the full-scale input levels, Input Amplifier
gain
and full-scale output levels for each INPUT SENSITIVITY
setting.
4-32.
Post
Attenuator. The Post Attenuator
is
a resistive
divider network controlled by the INPUT SENSITIVTY
switch and by the front panel slide switch that selects
dBV/LIN or dBm/600rl. With the slide switch in the
dBV/LIN position, the post attenuation
is
- 5
dB
or -
15
dB.
With
the switch in the dBm/600rl position, the attenuation
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