HP 9020 - Processor Stack Block Diagram

Theory of Operation 2-13
• A load board must be used in the top occupied slot (adjacent to the RAM boards) any time the
stack configuration
is:
a. One CPU, one lOP, and one 512K RAM card.
b. RAM is composed of all 1 Megabyte RAM boards and there are less than 6 RAM boards.
(The load board
is not required if other types of RAM are included in the stack, or there
are more than six 1 Megabyte
RAM cards in the stack.)
SYSTEM CLOCK
MEMORY PROCESSOR BUS
(MPB)1
NOTES
1 MEMORY PROCESSOR BUS INCLUDES:
ADDRESS,
DATA, BUSCONTROL,POWER
AND GROUND, SELF-TEST
MISCELLANEOUS CONTROL
2 MEMORY CONTROLLER
3 RAM BOARDS CAN BE 256K
512K,
OR PAIRS OF 1MBOA RDS.
ADE
4 REQUIRED WHEN RAM
IS M
UP
OF SIX OR LESS 1 MEG
BOARDS; OR ONE CPU, ON
AND ONE 512K RAM BOARD
ABYTE
E
lOP,
lOP BUS
CLOCK
BOARD
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l
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LOAD RESISTORS
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LOAD BOARD
4
CLOCK RAM
MC
2
RAM BOARD
3
CLOCK
RAM
MC
2
RAM BOARD
3
CLOCK
lOP
"-
IOP:~
lOP
BUFF ASSY
FINSTRATE
CLOCK
CPU
CPU
FINSTRATE
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THERMISTOR
Figure 2-7. Processor Stack Block Diagram
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