Theory
of
Operation
2-33
Beeper
The keyboard contains a programmable tone generator (beeper) that can play any of
255
tones
between
194
Hz
and
50
kHz.
This circuitry takes a 200-kHz clock from the microprocessor
and
divides
it
by two twice. The
resultant
50-kHz signal
is
then divided by an 8-bit divide-down value that has
been
previously
loaded into R11 by the
lOP. When the count goes to 0, the desired output feeds a control chip
which provides
an
output square wave to the beeper at the desired frequency. The divide-down
byte
is
then reloaded from the buffer registers,
and
the process continues.
The
lOP turns off the
beeper
by writing a divide-down byte of
all
l'
s to R11. The circuitry senses
this
and
inhibits the beeper. The beeper
is
a transistor amplifier with a diode for protection from
inductive feedback.
RTC/NVM Logic and Enable
The real-time clock (RTC) chip contains
16
four-bit locations that store clock
and
date information
that
is
initially loaded from the lOP. A
32.768
KHz
crystal oscillator provides the time base. A 4-bit
multiplexed data bus provides
I/O for the RTC chip.
Writing to R1210ads a 4-bit register address
in
the chip. The RTC data
is
then accessed by reads
or
writes of R9, either reading data from the addressed location or writing data to
it.
Once the initial
address
is
accessed, succeeding reads
or
writes cause automatic increments of the address. This
enables blocks of data to be read
or
written without updating the address from the lOP.
The non-volatile memory
(NVM)
chip contains
2048
eight-bit bytes of CMOS
RAM
used to store
configuration
and
service data. Writing a 16-bit address to R12
in
complemented form loads the
address of the
NVM
location. The data
in
that location
is
then accessed by a read
or
write of R13.
RTC
and
NVM
contents are listed
in
Chapter 3.
During power-off states, a nickel-cadmium
(NICAD)
battery assembly provides power to the RTC
and
NVM
chips for a minimum of
10
days. The circuitry which controls battery operation
is
described
in
following paragraphs.
The accuracy of the RTC
is
partially
dependent
on
the configuration, environment,
and
usage of
the computer. Worst-case clock deviation varies between
40
seconds per month
and
3 minutes
per
month depending
on
these factors.
Power-Up/Power-Down
Sense
Circuitry
The RTC
and
NVM
chips must
be
disabled when power
is
coming up or going down. Otherwise,
spurious data could
be
written onto the chips. When the power supply senses that the power output
is
out
of specification,
it
sends an interface clear signal to disable the lOP bus. This signal
is
translated
on
the keyboard electronics board
and
disables the chips.
When the chips are disabled, the circuitry enables battery input to the chips, maintaining the
memory data
and
keeping the clock running. During normal operation, the battery
is
being charged
by the
+ 12V supply.
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