Theory
of
Operation
2-15
Stack Motherboard
The stack motherboard interconnects the 12 board slots via the memory processor bus. The two
25-pin connectors at the bottom of the stack provide power
and
some control signals to the stack
motherboard. The stack motherboard has 12
LEOs that indicate the status of the boards when
module self-tests are executed.
Clock Board
The clock board provides clock signals to the processor. This board electrically interconnects to the
stack motherboard via a 9-pin connector. The clock board attaches to the stack motherboard with
two screws.
Power Interlock Switch
A power interlock microswitch causes power supply shutdown
if
the stack door
is
opened
with
power on. Shutdown results
in
all
RAM
data being lost. The power switch must
be
cycled to power
up the computer. The power interlock switch prevents damage to boards caused by their removal
or insertion with power on.
Cooling
A dc box fan
is
mounted at
one
end of the stack to draw cooling air through the stack. An air
controller
is
mounted
in
the stack. The air controller blocks air from circulating through the
open
area
if
the stack
is
not
filled
with boards
and
ensures that most of the cooling air
is
circulated
between the boards.
The fan has three speeds which are varied according to the temperature sensed on the secondary
board heat sink
in
the power supply assembly. Refer to the preceding Power Supply Assembly
description for details on fan speeds and temperature thresholds.
Memory
This subsection describes the organization of
RAM
memory within the stack.
It
also describes error
detection
and
correction, mapping, and healing.
Memory Organization - 256K Byte
RAM
Board
Up to
10
RAM
boards can be configured
in
a processor stack. Each board has a Memory Controller
(MC)
and
256K, 512K,
or
1 Megabyte of
RAM.
This section
will
cover the theory of operation of
the 256K board (Figure 2-8),
and
following sections
will
cover the other
RAM
boards.
The
MC
interfaces the memory
on
the
RAM
board to the
MPB.
The
MC
uses
27
bits of the MPB
logical address to locate the physical memory address on the
RAM
board. 12 bits of the MPB
address are used as part of the X
and
Y addresses. The other 15 bits select a mapper Content-
Addressable Memory
(CAM)
register. The mapper
CAM
register output
is
used to provide Chip
Select (CS) lines
and
3 more Y address bits for block selection. One of four chip select lines selects
one
of four rows of
RAM.
Each row of
RAM
has four 4K word blocks of memory, for a total of 16K
words (four 8 bit bytes per word). The row
is
actually comprised of
five
16K by 8 bit
RAM
chips.
Each word has
32
data bits
and
7 checkbits for error detection and correction. Data
and
check bits
are transmitted
on
the Memory Data Bus.
The 8-line Memory Address Bus multiplexes 15 address bits. The lower 8 bits comprise the X
address
and
are transmitted from the
MC
first.
The next 7 bits make up the Y address
and
are
transmitted next. The most Significant bit of the
Y address
is
ignored
in
the
RAM.
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