Testing
and
Troubleshooting
3-9
Self-Test Supervisory Code
The STSC verifies the integrity of the internal
liD
bus, tests the interfaces on
all
of the internal
modules, retests mapped-out memory blocks that previously failed the memory controller test,
and
reports the blocks that
fail
the retest. The STSC functionally tests modules that do not have
self-tests
and
the associated interfaces.
The following paragraphs describe the tests that the
STSC initiates
in
the computer.
Internal I/O
Bus
The internal
liD
bus
is
connected to the
first
lOP. A ribbon cable carries the
liD
signals from the lOP
to the computer motherboard. From the motherboard the cable
is
routed to the printer
and
then to
the keyboard. The motherboard transports the signals to the
liD
backplane connector. The
liD
backplane has three slots for mass storage controllers
and
four
liD
card slots. A ribbon cable from
the
DIM
connects to the top of the
liD
backplane.
liD bus failures generally
fall
into
one
of three major categories:
• One or more of the
liD
lines
is
open.
All
interfaces beyond the
open
line(s) respond unpredict-
ably.
• A component failure has occurred
on
a particular interface or interface control circuit. The
particular module responds unpredictably.
•
110
lines are shorted. This failure affects every interface. Each interface must
be
unplugged
in
turn until the problem
is
isolated
and
the bus functions.
The
110
bus
is
tested immediately before the initialization of the
110
subsystem. The test determines
whether or not the
110
bus
is
functional. Loopback sequences are initiated to each device before
command sequences are initiated. A loop back test writes a data value to a register
and
then reads
the value. More complex tests are initiated after loop back passes.
The
110
bus test progresses from the device which
is
electrically nearest to the lOP to the device
which
is
the farthest away. The possible locations of an
open
are narrowed down to somewhere
betweeen the last device that passed
and
the
first
device which failed.
Memory
At
powerup, any blocks which were
"mapped
out" by the memory module self-test are re-tested to
determine
if
they can
be
salvaged. If there are less than
32
single-bit hard errors, the memory healer
compensates,
and
the block
is
mapped back
in.
If
there are too many errors, the block
is
left
"mapped
out"
and
a message
is
issued that identifies the block that has failed.
The memory controller breaks up
its
physical memory space of
256
kilobytes into
16
logical blocks
of
16
kilobytes each. Each logical block
is
operated
on
as a unit. Individual blocks can be
mapped
to any part of the logical address space of the
MPB,
or the blocks can
be
completely
mapped
out.
Mapping out a block effectively makes
it
nonexistent by not responding to any logical address.
All
memory controllers, in parallel, perform a memory test
on
the
RAM
plugged into their cards. Bit
patterns are written into
all
RAM
chips including the Hamming bits. The pattern
is
written into the
entire memory,
and
then the pattern
is
read block by block.
If
an
error occurs, or
if
the memory
is
physically absent, the block
is
automatically
mapped
out.
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