2-48 Theory
of
Operation
The Poll Logic indicates when the controller
is
ready with or for data. It responds
on
the NIOD line
corresponding to its select code when prompted by the
NPOLL line. Synchronization logic assures
that this response does not begin during a poll cycle.
The Reset Timer
is
a shift register which functions as a digital one-shot to
reset
the microprocessor
and
then
all
resettable devices. Reset
is
initiated by either the NIFC (interface clear) line or by the
setting of
NIOD bit 5 of output register
RI.
Residing
on
the 8-bit microprocessor bus are the
8039
microprocessor, I/O registers, the
8876
controller via buffers, the ROM containing microprocessor instructions,
and
RAM
to hold
one
sector's worth of data. When data
is
written to the disc,
it
is
moved from the lOP to the
output
register latch from where the microprocessor reads
it
and
places
it
in
the sector buffer
RAM.
After
the sector buffer
is
filled,
the microprocessor reads the data from the
RAM
and
sends
it
to the
8876
where
it
is
serialized
and
sent to the disc. Data
is
read from the disc by reversing the process.
All
elements
on
the microprocessor bus communicate with the move-external instruction of the
processor. Strobe lines go to
all
of the elements on the bus except the
RAM
and
selectively enable
these elements at the appropriate time.
Other strobes clock or clear various flip-flops. When the
processor accesses
RAM,
strobe generation
is
disabled
and
RAM
is
selected via the RAM/Strobe
Switch circuitry. Then the same move-external instruction accesses any of the
256
bytes of
RAM.
The
8876
controller chip controls
all
of the serialization/de-serialization
and
ID
field verification
on
the disc. The Pre-Compensation circuitry inputs the serial write data produced by the
8876
and
pre-distorts
it
to correct for shifts
in
the apparent position of pulses on the disc.
The Phase-Locked Loop
(PLL) reconstructs a clock from the
encoded
pulses coming from the disc.
This reconstructed read clock
and
the original data pulses are sent to the 8876. The sync detect
circuitry switches the
PLL from
its
free-running, nominal condition to tracking
mode
when
a sync
field
in
the data pulses
is
detected. Margin detect circuitry detects when read pulses are
out
of their
nominal position during disc formatting.
Winchester Fixed
Disc
Drive I/O Card
Figure
2-25
is
a block diagram of the Winchester Fixed Disc Drive I/O Card.
All
lOP signals are
on
the left side of the diagram,
and
all
Winchester disc controller signals are
on
the right side.
The functions of the
I/O card are 1) to interface to the lOP, decoding
and
interpreting commands;
and
2) to interface to the Winchester disc controller, buffering data to
and
from the controller. A
50-pin ribbon cable interconnects the I/O card
and
the disc controller.
lOP interface lines
NIODO
through NIOD7 are buffered. NSTS, NFLG,
and
NBR are also driven
with buffers. The direction
and
enable lines are
READ
(direction)
and
MYPA
(enable).
MYPA
is
generated by the ANDing of PA2,
PAl,
PAO,
NPOLL, NIC4,
and
DEVI. The Winchester interface
is
assigned to select code
7.
NPOLL disables
MYPA
if
a poll
is
occurring. NIC4 prohibits the
generation of
MYPA
during a select code change. DEVI ensures that device
#1
(Winchester)
is
selected as required
due
to select code sharing.
An interface clear signal (IFC) from the
lOP resets
all
logic
on
the interface including the microp-
rocessor. IFC also resets the select code sharing hardware, indicating that device
# 1
is
enabled to
use select code
7.
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