HP 9020 - Page 62

2-36 Theory of Operation
The G signal is a disable signal that isolates the output of the alpha data buffer from the frame
buffer.
Frame Buffer
The frame buffer is composed of four static RAM chips that provide 2480 16-bit words. This allows
storage of 31 rows of
80 alphanumeric characters, or one full display data frame. The frame buffer
is normally written from the lOP, but can be read for diagnostic purposes. Data transfer can occur
both
in DMA or direct 110 modes.
The controller accesses frame buffer locations with 12 address lines. The location may
be accessed
to load
updated information from the lOP or to transfer data to the line buffer.
The WE line
is a write-enable that is high for a write to the frame buffer, and low when a buffer read
is required.
OE is the output-enable and is high when the frame buffer is being written or when data is being
transferred to the line buffer.
Line Buffer
The line buffer is an NMOS-II chip that provides a dual line buffer function. It consists of a word
counter, two 80-character shift registers, self-test circuitry,
and support logic. Although there are 16
data paths on the chip, the display requires that only 15 be used.
The line buffer transfers
an 80-character row from shift register 1 to the display while loading shift
register 2 with
another 80-character row from the frame buffer. When the transfer is complete, the
buffer toggles the registers
and begins shifting the contents of shift register 2 to the display while
reloading shift register 1 from the frame buffer. This process continues until
an entire frame has
been transferred to the display.
Timing signals from the display control the loading
and shifting of the line buffer registers. NW (new
word) signifies next character, NL (new line) signifies next row,
and NP (new page) signifies next
frame.
NP controls the address counters in the controller to ensure that the frame buffer is correctly
accessed.
LD is a clock from the controller that enables data into the appropriate shift register from the frame
buffer during load times.
The test signal (TST) puts the line buffer into self-test
mode when it goes true. Self-test mode can be
entered in two ways: 1) by pressing switch Sl, a momentary pushbutton switch mounted on DIM
and accessible at the bottom of the display, or 2) by software diagnostics. If the switch is used, the
manual test signal (MTST) goes true.
In either case, the TST line goes true. The line buffer has a
counter that generates a self-test pattern to the display
in response to TST. An error in the test
pattern
Clln be easily detected. The ERR line to the controller goes true when a line buffer error is
detected.