Inovance H3U Series - Page 200

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4
4 Instructions 4.5.4 Data Rotation and Shift
SFTR: Bit shift right
◆
Overview
When driving conditions are met, the SFTR instruction shifts a combination of bit elements with a length
of K1 from head address D to the right by K2 bit places, to accommodate a combination of bit elements
with a length of K2 from head address S that ll the higher bits. The K2 lower bits that are moved out are
discarded. The original values in the bit element combination S remain unchanged.
SFTR S D n1 n2
Bit shift right Applicable model:
H3U
S
Bit element
head
address
Head address of shifted bit elements
16-bit instruction
(9 steps)
SFTR:
Continuous
execution
SFTRP: Pulse
execution
D
Incoming
bit head
address
Head address of incoming bit elements
n1
Incoming
bit count
Number of incoming bit elements
n2
Bit element
count
Number of shifted bit elements
◆
Operands
Operand
Bit Element Word Element
System·User System·User Bit Designation Indexed Address Constant
Real
Number
S X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
D X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n1 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n2 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
Note: The elements in gray background are supported.
◆
Function
n1 bit variables from head address D are shifted n2 bit places to the right, to accommodate n2 bit variables
from head address S that ll the higher bits.
The instruction of the pulse execution type is generally used.
Example:
X20
ķ
M 3~ M 0
Overflow
ĸ
M 7~ M 4M 3~ M 0
Ĺ
M 11~M 8M 7~ M 4
ĺ
M 15~M 12 M 11~M 8
Ļ
X3~X0
M 15~M 12
M15
M14
X0
X1X2
X3
M0 M1 M2 M3 M4
M5
M6
M7
M8 M9 M10
M11
M12
M13
ĺĹĸķ
Shift of every four bits to the right
Ļ
ǒSFTRP X0 M0 K16 K4Ǔ
S
D n1 n2